Net class assignments

[Mat28]

Hello,
does anybody has an idea what this means in the schematic? When I assign a net to a specific net class with individual spacing and trace width for the pcb, the associated electrical wire in the schematic editor also gets drawn with the same properties. Is there a any switch or so where this behavior could be controlled?
M.

[mf_ibfeew]

See schematic-documentation: Schematic Editor | 7.0 | English | Documentation | KiCad , section " Managing netclasses in Schematic Setup"

You have two different netclass-dialogs:

• one in the schematic-setup–>project–>netclasses. These dialog sets the visual display of netclasses in the schematic (this is probably what you have done)
• and the other one in the board-setup–>design rules–>netclasses. These dialog sets the values for the netclasses on pcb-level: netclass clearance, track width, … (this is probably what you wanted to do)
• look at the exact headline-description in both netclass-dialogs and you will see the difference
• both dialogs share the same netclass-definitions and netclass-assignments.
• both dialogs are synchronized with the update board from schematic command

[Mat28]

Oh thanks, I was not realizing that the width refer to different elements ( electrical line vs trace). I could not imagine that in schematic is a need for line width. You poked me with my nose at it. Many Thanks now working!