In PCB, net assigment seems to work because I have “Resolve Net class: 5AMP” when trying to route my nets. But LOAD+ and LOAD- have a track width of default net ( PCB says “from board minimum trackwidth” ) and BAT+/PAN+ net have the correct track width ( PCB says “from netclass 5AMP”).
Something prevent PCB to use the correct track width for LOAD nets, I don’t know what and I don’t know how to find the problem. DRC check only give silkscreen overlap warning.
without having the project at hand: probably “LOAD+” and “LOAD-” are treated as “differential pair” and therefore the track width / gap values from the “differential pair” column are used.
Try to rename for LOAD_plus/Load_minus. (note: the “_P/_N” combination is also used as “differential pair” marker).
