NAND Flash interface routing

Hello guys,

I have a second thought about trace length difference when it comes to NAND flash. I come around some layout recommendation and it suggest that length difference between data signals do not exceed 400 mil ~ 10 mm. with controlled impedance of all signals 50 Ω.

But on most other places I cant find anything about trace length matching. Only controlled impedance.

What are your experiences about that, does in this case trace length matching really matter?

Afaik (I hope I’m correct)… :thinking:

If the impedance isn’t correct the signals between the flash and the MCU/CPU will have a hard time to stay within spec (raise/fall time, voltage levels, etc. pp.).

If the trace length is different the x-bit wide bus bits will be out of sync and when the transmitter sends 0x1010001 1 (8bit) the receiver might understand 0x1010001 1 or 0x1010001 0 (assuming one track of the 8 - the one for the least significant bit - is not the correct length).

Its two different things.


Read this document on PCB layout
25ns access times require some care


First of all, tnx guys.

So, MPU has programmable setup, pulse and hold time for read and write signals; and programmable timing.
NAND read timings are

My trace length difference is max 9 mm, with the longest trace 21 mm.
So afaik thats not concerning. But I wanted to be sure.

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NAND Flash always used to be and only the CS and RD/WR controls were critical.
These days there is also High-Speed NAND, which uses the source synchronous DRAM interface, see

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