Naming and Connecting Buses

[schlabs]

Hi everyone.
I am working in a big project with BGA and more than 300 bals. So i split the schema on 10 pages, and use the root to connect different buses.
To keep the root clear i name the bus with a short word, and name the bus with all elements:
For example:
hierarchical connection to bus: CNN
Bus label: Cnn{EthTEn EthTx0 EthTx1 EthRx0 EthRx1 EthCrsDv EthClk EthMdio EthMdc EthIrq EthRst EthRxEr Mb1Tx Mb2Tx Mb1Rx Mb2Rx Mb2De Mb1De PiTx PoTx PiRx PoRx PoDe PiDe 232Tx 232Rx PiLed PoLed Mb1Led Mb2Led PrnLed}

On the root i wire

When i use the tool to highlight the connection the pins of one sheet are well connected to the pins of another sheet.
But The DRC fail, not valid connection between bus and net element.

I solve partially adding the complete list of elements to hierarchincal label.
But this become unfriendly and unclear on the root because there are at least 4 buses with more than 30 elements each one.

There is a way to get the the hierarchical names short? Or keep the names on the root short? Thanks in advance to all

[mf_ibfeew]

You could use the Alias-definition for bus-names. (schematic editor–>schematic setup–>Project–>Bus Alias Definition).
See also the description in the official documentation (the bus-section is quite good):

Schematic Editor | 7.0 | English | Documentation | KiCad

section “Electrical Connection”, than scroll down until “buses”.

I have attached a example which shows the short busnames, no ERC- and DRC-error:
Bus_naming_tests_01.zip (30.6 KB)

[schlabs]

Thanks, works perfectly. Now i have zero errors and zero warnings