There have been a few posts about this sort of thing but I thought I’d bring it up again and see what happens.
I regularly connect some nets across layers with clusters of vias. I do this for high-current traces and power traces. The way I’ve been doing this in KiCad is to place the vias, and then put a small multi-layer zone around them and then route traces to this little via island.
I used to do a similar process in Altium to achieve the same effect, although I’d use regions instead of zones.
The reason I don’t just put a few vias down and only use traces to connect them is partly because it’s irritating to have to draw traces on all layers and partly because the reduntant track removal “helpfully” undoes my good work. On a side note, I know I can turn that feature off but I mostly like it for all other use-cases.
Anyway, I began imagining a more usable way to acheive my goal that would require less futzing. Maybe you could draw a little shape and then KiCad would automatically add vias at a predefined spacing and hole-size. Those shapes would exist on all specified layer. It would be kind of like a “compound” via or something. Then you route to and from it with tracks as you’d expect.
Maybe there’s another way that this could be done. Maybe there’s already a way to do it and I just don’t know about it.
You can turn off PCB Editor / Route / Interactive Router Settings / Remove redundant tracks, but toggling that checkbox is also not optimal. A quick option is to lock tracks in place. I think (have only briefly verified) that locked tracks are being ignored by this optimize / remove function.
But drawing a little zone for this, and then setting it to multiple layers is a quite reasonable solution. You can even put such a construction next to the PCB, (inclusive the via’s) and then just make a copy of it for each location you want to use it (and change the net name).
Using multiple via’s for high current tracks is a common practice. It may be worth a feature request for the Remove redundant tracks to not “optimize” these away.
Another option is to use some graphic lines with the same width as tracks. Graphic lines are becoming more integrated into KiCad, and graphic lines on a copper layer automatically become part of a net in KiCad V8. (I have not tried it myself though).
I did experiment with using rectangles and lines for this purpose. That was fine but I settled on using zones because I like the way you can set which layers they should be applied to. For graphic elements you have to draw one one each layer.
Hmm. I thought I replied to you already Piotr. That’s a good suggestion. Although I’m not super keen to use footprints without corresponding symbols. Managing symbols for these things doesn’t seem like a good idea either.
Taking in mind what you write about zones my suggestion of using footprints can be not so good. I expect problems with decisions about inner layers (but I’m not fluent in footprint possibilities in V8).
I also don’t use footprints without corresponding symbols and thought about writing something about it but I gave up. You don’t use symbols for vias. So may be you can treat placing such footprint like placing via (probably should be locked or there is may be other way to protect against being removed by update to schematic).
Also adding one pin symbol just near one VCC symbol (or making this connection in sheet corner) would be for me acceptable.
But without checking how with internal layers there is no idea to discuss this.
I like this idea. It is closely related to via fencing, I would say. I guess this is on the to-do-list but I don’t find a corresponding feature request at the moment.
I also have the same problem:
By purpose I want to have 2 vias connecting my power line.
But when I draw a top wire across the two vias, then the bottom connection gets removed.
Is there a simple way to turn off this “feature”?
If not, how do I file a change request?
To get high current capability you want the sum of the circumferences of all the vias to be at least as much as the width of the trace you’re dealing with. So one big via can be equivalent to a lot of little ones. Since the circumference is pi times the hole diameter of the via, it seems one via with a hole about half the trace width should do it. I think also with big vias the plating process is more likely to get good thick copper on the via walls.
It seems to me too simplified reasoning.
Initial copper is 18um and during plating it rises to 35um but in vias it rises from 0 to ?
I don’t know the technology details but if it is so that plating in hole rises from copper at it ends than plating in in the middle of the hole can be much smaller than 17u added to tracks during this process.
Yes, and the answer has already been given in the first reply in this thread. So what more do you want?
Drawing graphical rectangles is also not the way to go forward.
That would be a minimum indeed. the plated walls of vias have thinner copper then the tracks. This is inherent in the normal PCB production process. Typical values are 35um for tracks, and 17um for via’s. As a result when this circumference equals track width, the vias would get hotter.
I use multiple vias for reliability reasons.
As long as your circuits sits at room temperature and 50% humidity, one via is good enough.
But place your boards into an automotive application and you will experience an entire different world! I design the multiple vias in a way, that one can fail and the rest will still be enough for the current.
I have “remove redundant tracks” unchecked and as since 2017 configuration goes with me from version to version I even don’t remember if default it is checked or unchecked.
Well - the disadvantage is, that KiCad-DRC blames 2 lines of the same net on top of each other as an error (which in my opinion is not worth throwing an error). So I have to clean up the layout in order to get it DRC error free.
