Not sure why you're vehement insistence that schematic capture not work like every other ECAD package I have used for the past 30+ years.
It's not "vehement insistence." Its the recognition that "this is how Kicad works" combined with having been bitten by Altium's handling of this multiple flat sheet net handling. I think my question was, 'is it really so hard to just create a top-level sheet?"
I haven't used Altium so I can't answer for their handling of flat schematics but over the years I have used ViewLogic, Daisy, Cadence, Mentor, PowerView, Eagle and several more that I have forgotten. All these tools were/are capable of doing very complex designs using a flat schematic paradime.
Flat schematics with common signal names being the same net is the norm. It maps well into the PWB physical implementation.'
If you're drawing your schematics I'm a way that maps to the board layout, all due respect but your boards must not be very complicated. The last day job board I did is the size of a playing card but it's packed on both sides with all sorts of stuff, including a big FPGA, and attempting to draw a schematic that looks like the layout would be impossible.
We draw schematics so the human engineer or tech can understand the design.
You are missing my point. The flat schematic has all of the net names shown exactly as they appear in the board file. There is a one to one mapping. I am assuming that the hierarchical schematic produced net list has net names generated by the tools. If I print out a pdf schematic can I search it for a net name from the board layout and find it? I had to laugh at your comment on my boards not being very complicated. A typical board from my day job has 18 to 24 layers with several CGA components with 1150 to over 1700 pins, board to backplane connectors with over 1000 pins, wide length match differential buses running at over 300MHz DDR rates as well as a couple of 1.3GHz 12 bit ADCs on a 9 inch by 7 inch board. A typical schematic has over 40 sheets. I don't do the layouts for these boards but I am responsible for the signal and power integrity of the finished designs. I am using Kicad to do a couple of simple test adapters for connecting test ports to Logic Analyzers, JTAG test equipment and SpaceWire monitors, so I am laying out these boards as well as interfacing with the board house.
As to your point about drawing schematics to understand the design, I am very familiar with understanding complex designs using flat schematics. I just don't see any advantage to understanding a design because it was drawn using hierarchy. A block diagram and table of contents on the first sheet works pretty well in my experience.
[quote]Standard industry practice is to use on and off sheet symbols which show signal direction and references to connections on other sheets, usually automatically generated by the schematic tool. [/quote]Yes, and what's missing from EESchema is the way to generate those sheet references. But what difference does it make if it's a hierarchical off-sheet symbol or flat design symbol? (Again, I don't care, I just do what Kicad currently supports.)
[quote]"Channels" or multiple implementations of the same sheet don't map as well to physical implementation. I would rather have good tools for copying sheets, renaming nets and assigning reference designators.
Ah, but with channels, hierarchical sheets in EESchema really shine. I did an audio thing (monitor controller) with several identical inputs and outputs, and I made extensive use of hierarchy. I drew a page once and instantiated it several times. Much less schematic clutter, and EESchema easily handles making unique reference designators, local net labels and mapping higher-level signals to the lower-level instances. (Of course this feature exists in Altium and other tools.) So there is no need to copy sheets if you're making a channel-type design.