I’ve been unsuccessful in finding a good solution to making clean schematics on eeschema when number of connections increase. I haven’t found this covered on the forums.
At work, I use schematics where a single component with 1000+ pins won’t fit on a single page. (Large components span multiple schematic symbols.) On KiCad, I can’t seem to fit even relatively simple designs.
On KiCad I use hierarchy, but I find that I often can’t fit a level of hierarchy in one page. I’ve thought hard about how to partition a design into smaller chunks. I’m assuming I need to break myself of old habits formed from having used Cadence crap for too long; however, I can’t figure it out. I could make enormous (size) pages, but I’d prefer not to.
Using global net names seem dangerous and tedious: I would have to have multiple top-level “contents” pages and try to manage global net names manually. (The global net management will be impossible if I reuse any sheets more than once!)
How do others (if any) deal with complicated schematics on KiCad? How about large components with 1000+ pins? I wasn’t able to find the RFEs that address this, which makes me think I’m missing something. I’ve been using KiCad intermittently for almost three years now. I’m very impressed with the progress. I’d hate to see a fundamental limitation carry on.