I’ve been unsuccessful in finding a good solution to making clean schematics on eeschema when number of connections increase. I haven’t found this covered on the forums.
At work, I use schematics where a single component with 1000+ pins won’t fit on a single page. (Large components span multiple schematic symbols.) On KiCad, I can’t seem to fit even relatively simple designs.
On KiCad I use hierarchy, but I find that I often can’t fit a level of hierarchy in one page. I’ve thought hard about how to partition a design into smaller chunks. I’m assuming I need to break myself of old habits formed from having used Cadence crap for too long; however, I can’t figure it out. I could make enormous (size) pages, but I’d prefer not to.
Using global net names seem dangerous and tedious: I would have to have multiple top-level “contents” pages and try to manage global net names manually. (The global net management will be impossible if I reuse any sheets more than once!)
How do others (if any) deal with complicated schematics on KiCad? How about large components with 1000+ pins? I wasn’t able to find the RFEs that address this, which makes me think I’m missing something. I’ve been using KiCad intermittently for almost three years now. I’m very impressed with the progress. I’d hate to see a fundamental limitation carry on.
Just out of curiosity, what page size are you using?
And why is that?
Might also be interesting to know what text sizes your symbols have and what pin to pin dimension for say a resistor is like to get an idea for where you are?
I’ve been with KiCAD not as long as you have and in that time haven’t seen it mentioned that people deal with such large and complex designs… you might be pushing the envelope there and it will be interesting to see the discussion of this, that’s for sure.
B size is the biggest practically printable size in the office. Large format printers are not as widely available. Similar on screen too.
Any more content on one page starts making it difficult to follow the true intent of what is happening. My view of schematics is like the programming rule of thumb of “any one function should fit in a screenful”. Hierarchy covers some of this, but not all.
I’ve started with some of the symbols already on the github library, so my library is similar in size to what’s out there. I’m not trying to change that. Pin pitch is 0.1" on grid.
I hope so. I’m excited to see KiCad develop into a very usable package. I’m happy to help mostly by giving it a real-life use and providing feedback. My view compared to Cadence tools is: Support is much more productive here (source helps too); software is still lightweight; bugs are comparable. You can understand it’s a lot more frustrating when you pay $25k/year for a seat and you hit bugs regularly and have to fight to get past first level of support!
While we’re on the topic of pushing the envelope, here are some features I see as worth considering:
Library management – I think someone else is covering this recently in the thread. It hasn’t bugged me yet.
Constraint management; This can get hairy, but a very little goes a long way. For example, length tuning that’s already in 4.0.x combined with per-net or per-class rules is part of the way
Support for multi-part component symbols, multi-page schematics (why I opened this topic)
Support for spreadsheet-based design! This is still in its infancy for the other guys. It may be a great opportunity for KiCad to stay ahead. The motivation is that as complexity gets pushed into ICs, the schematics start to slow us down. When I tried this three years ago on Cadence, it was still too buggy for prime time. I’m sure they’ve gotten better. In this approach, you make connections more like a spreadsheet. You can make schematic blocks to use stuff that’s better represented there. You can auto-generate schematics from spreadsheet or skip schematics all together. (I prefer having the second view.) Look at http://www.cadence.com/products/pcb/system_architect/pages/default.aspx for more.
I just tried it on 4.0.1 on MacOS: I made two symbols. “largeparta” with pins 1-5 and “largepartb” pins 6-10. I can’t get past the annotator with two parts having the same RefDes. Annotator window keeps popping up when I try to netlist or run CvPcb. I can’t convince it to generate a netlist with conflicting RefDeses, even if I assign Footprint fields in eeschema. This is with simple case of both symbols on the same sheet. Do you get this to work on KiCad?
This will get ugly very quickly. I would like some sane order to my RefDeses maintained as I keep updating schematics.
Agreed. Global signals have a very specific place, and no more. I’m finding hierarchy isn’t enough to boil schematics down to a single page. I have not seen a good justification of the single-page limit, or a good explanation of how to handle complexity in this paradigm. Is anyone aware of an RFE open, or should I start one?
Just highlighting the above again, as it’s easily missed.
That script allows you to get annotation depending on the position of devices in the layout and will communicate that back to the schematic, without screwing up.
Thanks, I was hoping you’d come by this thread as you deal with this on a daily basis.
when you break up your part into multiple units you can place the unit in a sheet
for usb, serial, Ethernet, jtag etc etc
rarely need to have signals leave the page
it becomed less of a problem
one problem is that kicad dont support buses composed of arbitrary names
lika a bus DDR
its very helpful to have those types of buses within the very same page.
bus content definition typically is a text file you can edit with any text editor and context as shown above
A3 i use as page, i like big pages and want to have all that belong related to one page
splitting same logical function up in multiple pages because of space constraints makes it harder to follow the schematic and more likely for errors when you cant see the relevant design in one page.
I think I get it now. @NikB and You need multiple schematic sheets with a local labels to connect them. Just like in “other commercial software called AD”.
In KiCad, there is no problem to put some more hierarchical sheets at any level making local flat hierarchies, but to connect them they need to use global labels. But you have to avoid that for some reason.
I haven’t seen any more development on this topic. That’s why I had posted the question.
After having used Kicad for another year, I am convinced: this is not a limitation of the way I’ve been conditioned to think by commercial software. This is a serious oversight in Kicad’s part, and it seriously limits its usability in even moderately complicated designs.
If nobody sees an open wishlist or bug report, I can file one.
I think there is confusion over the terms “page” and “sheet”, which in KiCad are exactly the same thing. Historically that makes sense, because a sheet was drawn on a single piece of paper which corresponds to a printer or plotter "page.
So I guess the OP is talking about having “sub-pages” per sheet, which are electrically all in the same sheet, but when printed would appear as separate pages. It might be useful, but I wouldn’t put it as essential - depends on user I suppose.
I originally posted this question to try to figure out how people deal with complicated designs in Kicad. I’ve not seen a satisfactory answer. I’m with nicholas that this is a problem.
I’ve considered using bobc’s suggestion of having multiple pages on the same schematic canvas. Kicad doesn’t offer a nice way to print that, though. It just crops everything outside the frame.
For a simple design, I thought this over many times; I can’t make the top level any smaller (using hierarchy liberally.) I still had to bleed off the edge of the page as shown below:
About making stuff global as a workaround: it’s not a workaround . Global isn’t appropriate for many signals. Consider an Intel CPU with 8 DIMMs in 4 channels. If you make many of the DIMM signals global, you’d short channels to each other. However, this is one of those cases where it’s going to take more than an 11"x17" page to get everything down at each hierarchy level. You can’t even fit a single Intel CPU on a single page.
Do you have some suggestions on how this could be fixed? From what I can see you want to be able to control the relationship of sheets, so that if you had sheets A B C D E you can say “A B and D all share local labels while C and E are completely independent”.