Multiple sheets at same hierarchy level


#1

I’ve been unsuccessful in finding a good solution to making clean schematics on eeschema when number of connections increase. I haven’t found this covered on the forums.
At work, I use schematics where a single component with 1000+ pins won’t fit on a single page. (Large components span multiple schematic symbols.) On KiCad, I can’t seem to fit even relatively simple designs.

On KiCad I use hierarchy, but I find that I often can’t fit a level of hierarchy in one page. I’ve thought hard about how to partition a design into smaller chunks. I’m assuming I need to break myself of old habits formed from having used Cadence crap for too long; however, I can’t figure it out. I could make enormous (size) pages, but I’d prefer not to.

Using global net names seem dangerous and tedious: I would have to have multiple top-level “contents” pages and try to manage global net names manually. (The global net management will be impossible if I reuse any sheets more than once!)

How do others (if any) deal with complicated schematics on KiCad? How about large components with 1000+ pins? I wasn’t able to find the RFEs that address this, which makes me think I’m missing something. I’ve been using KiCad intermittently for almost three years now. I’m very impressed with the progress. I’d hate to see a fundamental limitation carry on.


#2

Just out of curiosity, what page size are you using?

And why is that?

Might also be interesting to know what text sizes your symbols have and what pin to pin dimension for say a resistor is like to get an idea for where you are?

I’ve been with KiCAD not as long as you have and in that time haven’t seen it mentioned that people deal with such large and complex designs… you might be pushing the envelope there and it will be interesting to see the discussion of this, that’s for sure.


#3

US B size: 17"x11"

Two reasons:

  1. B size is the biggest practically printable size in the office. Large format printers are not as widely available. Similar on screen too.
  2. Any more content on one page starts making it difficult to follow the true intent of what is happening. My view of schematics is like the programming rule of thumb of “any one function should fit in a screenful”. Hierarchy covers some of this, but not all.

I’ve started with some of the symbols already on the github library, so my library is similar in size to what’s out there. I’m not trying to change that. Pin pitch is 0.1" on grid.

I hope so. I’m excited to see KiCad develop into a very usable package. I’m happy to help mostly by giving it a real-life use and providing feedback. My view compared to Cadence tools is: Support is much more productive here (source helps too); software is still lightweight; bugs are comparable. You can understand it’s a lot more frustrating when you pay $25k/year for a seat and you hit bugs regularly and have to fight to get past first level of support!

While we’re on the topic of pushing the envelope, here are some features I see as worth considering:

  • Library management – I think someone else is covering this recently in the thread. It hasn’t bugged me yet.
  • Constraint management; This can get hairy, but a very little goes a long way. For example, length tuning that’s already in 4.0.x combined with per-net or per-class rules is part of the way
  • Support for multi-part component symbols, multi-page schematics (why I opened this topic)
  • Support for spreadsheet-based design! This is still in its infancy for the other guys. It may be a great opportunity for KiCad to stay ahead. The motivation is that as complexity gets pushed into ICs, the schematics start to slow us down. When I tried this three years ago on Cadence, it was still too buggy for prime time. I’m sure they’ve gotten better. In this approach, you make connections more like a spreadsheet. You can make schematic blocks to use stuff that’s better represented there. You can auto-generate schematics from spreadsheet or skip schematics all together. (I prefer having the second view.) Look at http://www.cadence.com/products/pcb/system_architect/pages/default.aspx for more.

For an example or a moderately-complicated part, take a look at the schematics here:
http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx
Download the user guide at the bottom of the page; there are schematics at the end that break the component across pages. (I’m not saying this is the right way; just an example.)


#4

I feel your pain :slight_smile: Once you start working with FPGAs that have 484 balls and such, you must break up the symbol into several units, or else the design becomes unmanageable. And yes, 11x17 (or the Euro equivalent) max, please, none of this drawing the schematic on D-size paper and expecting to be able to read it when printed on B size!

So for starters, for those big parts, you have to ensure that they all share the same reference designator. The annotator will probably screw up if you have part of the chip on one page and part on the other, so assign both the same reference designator and don’t allow Kicad to re-number already-annotated parts. (Also, there is a script someone wrote which allows for a geographic re-numbering from pcbnew which back-annotates to the schematic, so the two are in sync.)

And I never use global nets except for power, so this requires that you bring signals through the hierarchy with hierarchical labels. And in the instantiating sheet, you need to add the hierarchical pins to each sheet instance’s symbol. So it’s a bit of work, but it ensures that all of your expected connections are made, and that you don’t inadvertently connect the wrong things together because you used the same global label by mistake.


#5

I just tried it on 4.0.1 on MacOS: I made two symbols. “largeparta” with pins 1-5 and “largepartb” pins 6-10. I can’t get past the annotator with two parts having the same RefDes. Annotator window keeps popping up when I try to netlist or run CvPcb. I can’t convince it to generate a netlist with conflicting RefDeses, even if I assign Footprint fields in eeschema. This is with simple case of both symbols on the same sheet. Do you get this to work on KiCad?

This will get ugly very quickly. I would like some sane order to my RefDeses maintained as I keep updating schematics.

Agreed. Global signals have a very specific place, and no more. I’m finding hierarchy isn’t enough to boil schematics down to a single page. I have not seen a good justification of the single-page limit, or a good explanation of how to handle complexity in this paradigm. Is anyone aware of an RFE open, or should I start one?


#6

[quote=“berkakinci, post:5, topic:2632”][quote=“me”]
you have to ensure that they all share the same reference designator[/quote]

I just tried it on 4.0.1 on MacOS: I made two symbols. “largeparta” with pins 1-5 and “largepartb” pins 6-10. I can’t get past the annotator with two parts having the same RefDes. Annotator window keeps popping up when I try to netlist or run CvPcb. I can’t convince it to generate a netlist with conflicting RefDeses, even if I assign Footprint fields in eeschema. This is with simple case of both symbols on the same sheet. Do you get this to work on KiCad?
[/quote]

Ah, there’s the problem – you made two different symbols. Kicad won’t let you annotate two symbols with the same reference designator.

What you need to do is to make a multi-unit symbol. In the schematic library editor, after you choose to make a new symbol or edit an existing symbol, click the icon that has ABC and an op-amp and gear. This opens the Properties dialog. Under the “Options” tag, look for “Number of Units.” For a symbol with two parts (like a dual op-amp), set that to two. For your big part, set that to however many different symbols you want. Also, make sure that “All units are not interchangeable” is checked.

Now your menu bar on the top will have a drop-down list with “Unit A” showing. Pull down on this, and you’ll see four units if you’ve defined your symbol to have that many.

Start drawing the symbol’s outline. Note, though, that as you draw lines and such, you have to make sure that in the “Sharing” option for those things, the “Common to all units in component” option is not checked. (Double-click a line or arc to see its properties.) Otherwise, as you select the different units, those lines will appear for all. There is a similar option for pins (double-click on a pin, look for “Sharing”).

You will quickly see an annoyance: the reference designator and the value fields will be in the same place for all units. This means that in some units, the refdes and value might be in a bad location. Don’t worry about that, because when you place the individual units on the schematic you can move those two fields to a better location.

Another annoyance: you can’t copy and paste between units.

When you’re done editing, save the symbol to your favorite library. You should be able to place the different units on different sheets, give them all the same ref des, and the netlister should be happy.


#7

Thanks. I will give that a try.


#8

@berkakinci
Just highlighting the above again, as it’s easily missed.
That script allows you to get annotation depending on the position of devices in the layout and will communicate that back to the schematic, without screwing up.

@Andy_P
Thanks, I was hoping you’d come by this thread as you deal with this on a daily basis.


#9

when you break up your part into multiple units you can place the unit in a sheet

for usb, serial, Ethernet, jtag etc etc

rarely need to have signals leave the page

it becomed less of a problem

one problem is that kicad dont support buses composed of arbitrary names

lika a bus DDR
with clk+,clk-
dqs+,dqs-
addr[12…0]
data[15…0]
DQM
RESET

etc
its very helpful to have those types of buses within the very same page.
bus content definition typically is a text file you can edit with any text editor and context as shown above

A3 i use as page, i like big pages and want to have all that belong related to one page
splitting same logical function up in multiple pages because of space constraints makes it harder to follow the schematic and more likely for errors when you cant see the relevant design in one page.


#10

Multiple sheets at same hierarchy level is a definite missing feature.


#11

You mean on a ‘root’ level…?


#12

At any level.
(why do posts have to be >20 chars?!)


#13

All hierarchical blocks are limited to one sheet, regardless of level.


#14

I think I get it now. :innocent: @NikB and You need multiple schematic sheets with a local labels to connect them. Just like in “other commercial software called AD”.
In KiCad, there is no problem to put some more hierarchical sheets at any level making local flat hierarchies, but to connect them they need to use global labels. But you have to avoid that for some reason.


#15

I know (123456789ABC)


#16

It creates an unnecessary level of hierarchy and an extra sheet.


#17

Am I correct that signal on two sheets at a lower level, different names and exposed by hierarchical labels, can be safely joined at the next level?


#18

Just to clarify. If you have two sheets A and B instantiated in a higher-level sheet C, and you have a signal coming out of A on a hierarchical pin, and you have an input signal into B on a hierarchical pin, and if you connect those two hierarchical pins on the sheet instances A and B in C, then yes, those signals can be safely joined together.


#19

Yes

this is a major pain/drawback

you should be able to have multiple pages on same level and select them with small tabs att the bottom in the same fashion as you select pages in excel

same signal names within this same level should automatically connect

lack of multiple pages on same level is a major drawback in kicad

anyone knows if this is on the wishlist already ?


#20

I haven’t seen any more development on this topic. That’s why I had posted the question.
After having used Kicad for another year, I am convinced: this is not a limitation of the way I’ve been conditioned to think by commercial software. This is a serious oversight in Kicad’s part, and it seriously limits its usability in even moderately complicated designs.
If nobody sees an open wishlist or bug report, I can file one.