Those bigger pads are also good for dumping heat on the non-EP versions of the package.
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This seems to be the package @drm requires. Iām curious to know the name of the component so the Data sheet footprint name for that component can be checked.
Aha. I did not have that library included and needed to find it. But I have now done so and it confirms my āvisualā of your image: This one has pads 0.25 mm wide.
Butā¦if the pin pitch is 0.5 mm, then do you think that the pad width and creepage dimensions need to agree precisely with the IC datasheet? Wowā¦the ADP1621 datasheet shows a min-max pin width of 0.15-0.30 mm. So how can we make pads which agree precisely with that?
That sort of example is what the discussion between the Librarians in the GitLab link above seem to be centered around.
The Jedec tolerances are from .17 to .33, much as you comment.
Iām not technologist. My personal opinion (only opinion) in this subject is different. Add word āprobablyā to each of following sentences.
For surface tension pads not extending too much out of 0603 element ensures negative feedback so element position is corrected during soldering. Too big pads extending out of it gives positive feedback with the result that element can be shifted toward one pad and then stand up.
The bigger corner pads at MSOP-10 footprint work the same - they work against holding IC in correct position (pad tries to position the leg in pad center) but there are 6 additional pads that work pro correct positioning and they win.
The corner bigger pads function is to make mechanical strength better for example if device drops on the floor. If you want to avoid battle between corner pads and internal pads and decide to have all pads the same width than to make mechanical strength as big as possible you should make pads as wide as possible. Using ICs with 0.4mm raster pads I use clearances smaller than 0.2mm. Footprints with big bottom GND pad ensure good mechanical strength. I understand that having no bottom pad someone could decide that to ensure mechanical strength pads have to be as wide as possible. May be the footprint was made based on datasheet of IC clearly destined to be used in cell-phones when you consider dropping at floor sometimes and probably 0.15mm clearance isnāt anything unusual there. Also corner bigger pads will be against compactness what in cell-phones is probably important parameter. So the decision of fully use assumed clearance of 0.15mm can be rationale.
As this way footprint definition depends on your product destination I think using our own footprints simplifies the task.
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It wasnāt me. It the OP - @drm .
I only did the footprint modification and raised the MR on GitLab.
Ah, my apologies @greg_m.
Iād like to give the excuse that my scroll finger was tired while finding the OP, but I fear it was just brain fade.
Iāve edited the above comments.
No worries @jmk . Iām not offended 
I just couldnāt answer your question and provide the exact name of the component used so it can be checked against the datasheet.
For my quick research there are variants of this package with and without a thermal pad. Those without thermal pad it says MSOP-10 indeed. So looks like it is probably correct what OP is asking about.
Except the TI, Analog and Allegro contradict.
It is a great shame that manufacturers, after spending all that time and money designing the chips and packaging, canāt seem to make just a tiny little bit more effort on the nomenclature.
I suppose their thoughts are āit took us a lot of effort to design, so weāll make sure it takes you a lot of effort to useā 
.
I am using the MSOP-10 with a MCP33131D/21D/11D-10/05. It is an ADC with SPI. OP has been edited to include the additional information.
Nope, it was PCBWay that bounced the gerbers on review. But I think AllPCB did it in some previous designs. In some ways it would have been better if they had bounced it too. I would have been alerted to fix it sooner.
My intention is that this footprint be used for my own hand soldering. I am holding the IC with tweezers in one hand as I hold the soldering iron in the other. It is fair enough that it might not be the best footprint for mass production methods.
Iāve learned a lot from this thread so far . . . thank you.
Wellā¦ in the old days (these days are "good"er), all of the electrical design tools would become instantly and unbearably onerous, at the first moment that you discover that you need to create a new symbol or footprint. And usually that happened about three seconds into any new design. All of the symbol and footprint libraries were hopelessly inadequate.
So from my perspective, things have improved a lot, and KiCAD as open source, and with text readable files, is simply fantastic.
I once designed a MIMO array for acoustic holography, in Python and had it write the PCB file as well. That was GEDA but it works more or less the same way for KiCAD.
Now, here we are in the age of KiCAD, it is improving all the time, there is a large user population, and companies all actively supporting the symbols and footprints libraries. Life is grand.
The only thing I am missing now, is that I have not tried the spice simulations, but only for fear lest it all become tedious again.
The main thing here is the SMT technology, and as we know, the technology of manual soldering of SMD does not exist. This type of case, like other cases for surface mounting, implies the use of a robot with machine vision for precise location data. If we consider the application of solder paste through a stencil, there too, the size of the apertures is not 1 to 1 to the size of the pad because the amount of paste is regulated by both the size of the aperture and the thickness of the stencil. The conclusion is very simple: always check the dimensions and recommendations of the microcircuit manufacturer both by the stencil and by the landing site, and the smaller the step or size of the component, the more critical it is.
One of the posters here sometimes solders parts on by hand, and I recall from some years ago someone who hand soldered large FPGAs.
such technology does not exist, this does not mean that it cannot be soldered, but without violating the technology, there is no. The technology involves installing a microcircuit on solder paste and melting it in a furnace along a profile. During production, repeatability is needed, no defects, and speed (time). I will tell you more, you cannot even solder an SMD resistor with a regular soldering iron) when touched with a soldering iron, a thermal shock occurs, which affects the component, etc., and the absence of the human factor ā¦ if you need to assemble a porta-type but follow the technology, then manual manipulators with a microscope are used, usually digital. With such manipulators, you can install 0402 and other components with a step of 0.3. Then the board is sent to the oven, after which the output components are installed, etc. There are a number of components that cannot be soldered physically with a soldering iron, ranging from active BGA LGA to regular pins, for example ( DS1025-07-2*20P8BS1-B) But at the same time, they all solder perfectly if done according to the technology
@drm - if you are still interested in this - there is a discussion on the Merge Request page on GitLab:
Long story short - looks like the JEDEC paper says max pin width (including tolerance) is 0.33mm, so the spacing we have as the moment is correct based on the JEDEC spec.
Lots of manufacturers specify the pin width 0.27 to 0.30 max. And some even for 0.33mm pin width advises 0.30 pad width.
However seems like we already have two very similar footprints to what you need:
VSSOP-10_3x3mm_P0.5mm
TSSOP-10_3x3mm_P0.5mm.
They may be good for your needs.
Of possible interest; the IC drm is using has on its data sheet:
Suggested pad width .3mm and leg width tolerance .17mm to .33mm.
Thank you, I just read through the discussion. I posted a suggestion that that 0.2 to 0.15 crosses a threshold in terms of where it can be assembled should be a consideration too. It seems to me the right answer is to include two variants in the library.