Hey all,
I’ve been busy working on a little project, and have removed all but one ERC error, that I cannot figure out.
Looking at other forum posts, I see they actually have visually multiple nets attached, but I do not and know not of which ones.
In the screenshot you’ll see an LMH-7322, which has two power pins, called VCCO. This shouldn’t be a NET, just the name of the pin. Its on PIN1 and 18 (top of my head, pin 18 is an invisible pin on the same location, cause we don’t have symbol pin mappings yet :p)
Also, I have a power plane for +2v5. All chips (4 in total, or rather, 2 chips, with 2 units each) have a few of these +2v5 (and also -2v5) rails.
Nothing is giving an error, except this VCCO and +2v5 thing. Looking at the schematic file with a text editor, I don’t spot anything obvious either, just the pin names.
I’ve tried to add a net-tie, just to see if it would matter, but alas. Interestingly, when I was looking at the same file on my laptop yesterday, it was puking on U2B, but on my Desktop right now, it’s U2A. But still only 1 error shows.
Since I’m a new forum member, I can’t post the schematic yet, https://gitlab.com/olliver/lapod/-/raw/add/lapod_logic_analyzer_breakout_and_pods/pod_lmh7322/pod_lmh7322.kicad_sch?ref_type=heads&inline=false but note that this is my WIP stuff, so will get force-pushed a lot and eventually removed from that location
P.S. be gentle, I am not an EE, far from it even