I have created a PCB layout for an H-bridge. I am using two SiZ340DT MOSFET ICs from Vishay (https://www.vishay.com/docs/62877/siz340dt.pdf), which consist of two MOSFETs internally connected to form a half-bridge.
I have some general routing questions
There is a footprint recommendation in the data sheet, which I have used to create my footprint.
My first question is, why are the pins of D1 or S2, for example, not combined as one area in the footprint? This does not only apply to this MOSFET but to all MOSFETs in similar packages in general. Would there be any problems when assembling the board?
I have used power paddles for routing the H-bridge. What are those yellow/gold areas around the pads? Is it exposed copper or hidden copper under the soldermask?
In PCB Editor Appearance window (at right) Layers tab you can switch on/off visibility of each layer. That could help understand what is what.
It looks that at 3D view you have blue F.Mask so hidden by mask copper looks blue.
Those gold is exposed copper.
How much of copper is exposed depends of Solder mask clearance set (see File-Board Setup-Board Stackup-Solder Mask/Paste). You should check your PCB manufacturer for the minimums you can use there. It depends on how precise they are when putting solder mask at PCB.
I agree with Piotr that the yellow/gold areas are probably exposed copper. Also I think the gray areas (that I think you are calling pads) are probably where solder paste is expected to be applied.
Check your data sheet to see if you should create a “window pane” solder paste pattern on those areas under the H-bridge packages so when it is reflowed the chip doesn’t float up on a big ball of solder pulling the edge contacts away from their connections. I don’t have the experience SMT layout peculiarities to be able to say if my concern is valid or not in your case.
BTW, you are asking about advice on D1 or S2, but no where in your post do you tell us which components are D1 or S2…
They are the names of the pin functions of the component in the datasheet, for example pins 5…7 = S2.
As for the original question, I agree what was said: the pins have been connected with continuous copper which is under the light grey paste and as yellow bare copper, and also under the mask. Blue is the mask. The mask clearance looks quite large. The copper areas under the pads are indeed continuous large areas for the pins connected together, but being exposed by large mask openings isn’t necessarily a good thing. Now the pads (pins) of the component don’t have individual copper pads, but one large pad and paste area. This may be more problematic for the SMT process than not having a continuous copper fill.
You should really find out the minimum mask clearance and also the minimum mask width (web) and try how they would look.
If I understand you correctly you are asking why you do not have the drain of each FET connected to the source of the other FET? Doing one as they do makes sense. The one common connection is usually called the “switchnode”. But if you you do both then your input + supply is shorted to your input - supply. That would make no sense. But maybe I misunderstand you…in which case please post a schematic image to help explain what you are looking for?
Thank you for the answers. You were right and in the global setting I set the Solder Mask Clearance in the Board Setup under Solder Mask/Paste to 0.2mm. Now I have set it to 0.05mm and it looks better.
Maybe I asked the question with D1 and S2 etc. incorrectly.
As you can see in the picture, we have 3 contacts and an area for D1 and for S2 also 3 contacts. Why didn’t the manufacturer like Vishay or Diodes Incorporated just connect the contacts from the beginning? More or less as indicated in the picture? You would have a larger surface area, which would be better for current-carrying capacity or heat dissipation, wouldn’t it?
Two educated guesses from my side on this: There could either be a problem in packaging so it has to be like this to get the FET into its plastic housing. Or what also could be the case is a problem with soldering if you have the big pad directly connected to the smaller ones, e.g. the big one pulls the solder away from the smaller ones etc and the manufacturer does not want this as it could lead to not meeting some characteristics.
Sounds logical that there could be problems with soldering.
Actually, I should start a new thread for the question because it’s a bit off topic, but for simplicity’s sake I’ll put it in this thread.
I want to have the board manufactured by JLCPCB. I use DGD0506A in MSOP-10 package as MOSFET driver. I have taken the capabilities from the JLCPCB site and added some extra to make sure I will always stay away from the worst possible constraints.
The pads for the MSOP-10 package have a width of 0.3mm and the patch pad size are 0.5mm. I wanted to use a track width of 0.3mm because it looks better and the track would be exactly as wide as the pad. But I can only route one track with this width and the others not, because I would violate the DRC rules. Even if I set the minimum clearance in the board setup to 0 mm, it doesn´t help. Where I can set the clearance of the track?
Currently I have routed the MOSFET driver with 0.2mm tracks.
It was clear for me. But as I don’t know the answer …
Not sure, but may be…
Having 8 identical pads ensures symmetric during soldering. If 3xS2 and 3xD1 would be one big pads may be the surface tension during soldering can shift IC out of its intended position.
you also have to set the net classes (left side of the last picture) to your wanted clearance. kicad always uses the biggest clearance value of net classes vs board constraints.
These are both on the right track. A symmetrical layout for the pads does generally reduce the incidence of soldering problems and makes the part more tolerant of less than perfect soldering processes.
Also, there is a lot of work that goes into such a package to trade off cost versus function versus reliability. Power FETs generally have pretty severe thermal cycling just by nature of their application. and all the attachments both in the package and from the package to the PCB need to maintain integrity for many thermal cycles.
Finally, this package probably contains two die with connections on both sides of the die. The thermal and electrical performance is to some extent limited by the top side connections which must be brought down to the package bottom.
Apologies if I’ve misread this, but consider double checking the pin 1 placement on this footprint. At the moment it looks like you generated pin numbers from the bottom view of the component, which means they will be backwards when you actually load the part.
You are absolutely right and have saved me from making a huge mistake. I mirrored the footprint and now it should be fine. I still have to adjust it in the layout editor.
