Missing Soldermask Clearance with Vias

My Kicad PCB is almost ready to be made by 4PCB but I am using their free DFM and I am getting 52 errors on Missing Solder mask Clearance. It is also saying “All component holes should have soldermask relief”.

All power traces (3.3V and GND) are different from default design rules, have 20 mil track width, 40 mil via diameter, and 20 mil via drill size. I tried lowering the drill size from 20 mil to 14 mil but that didn’t help. I clicked Edit All Tracks and Vias and Clicked “Set tracks and vias of the current Net to the Netclass value” and it did not help. I also pressed “E” on the keyboard manually while the mouse hovered over the “power” vias.

I changed Dimension -> Pads Mask Clearance from 0.0078 to 0.006 and 0.085 but I didn’t have to change this in my smaller project that passed all 4pcb DFM tests.

A smaller PCB that I created has with the same via drill size, via diameter, and track width and there were no problems with the 4PCB DFM. Maybe there is a way to reset vias? There is something not right. My Kicad version is 4.0.7 and I am using Windows 7.

Have you selected “Do not tent vias” in the gerber export settings?

Thanks for the reply.

“Do not tent vias” is unchecked.

I was able to get all problems solved after switching to 14 mil drill diameter and clicking “Edit All Tracks and Vias -> Set all tracks and vias to their Netclass value”. I’m not sure it worked every time but it did work several times. I was also able to get a 17 mil via drill size working. However I’d like a minimum 20 mil drill diameter so that it can handle up to 1 A of current. It is frustrating to not see larger via drill sizes don’t pass 4pcb’s DFM file check.

The Netclass set in “Design Rules -> Design Rules Editor” has a Power Netclass. It looks like there may be a bug. However when I view the Gerber files from within Kicad I see soldermask over the vias. I think that is what 4pcb wants, so I’m not sure what is happening.

It seems their DFM software assumes that a pad with a drill size above a certain diameter is a through hole pad and therefore they expect the pad to have solder mask clearance. Since it’s difficult, and not guaranteed, that holes this size will remain tented.

If you really want the larger vias you will have to bypass their DFM and submit your board with an engineering note explaining that those are intended to be tented vias. Alternatively you could use two or more smaller vias to get the current capacity you are looking for.


1.21GW’s explanation sounds very plausible.

As a workaround you can easily draw multiple small vias for a single high current trace, or make your own via’s from a regular through hole pad, with solder mask, clearance and everything.

Sounds like multiple vias is an okay solution to this problem. Thanks for the advice.

And if you use a regular through hole pad with solder mask, clearance, and everything you can call it a test point! :smiley:

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That is creative.

not yet 20 characters…

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