Hey everyone, I am working on my first pcb ever. I do have a degree in electrical engineering but never designed my own pcb as I ended up on the software side of things and never bothered with hardware. So this is my first time. I do understand the fundamentals of linear circuits, transmission lines, noise, emi… but i completely and fully lack practical experience. So expect many beginner issues.
The design idea is a 8 microphone linear array on which i want to experiment some microphone beamforming on.
I would love to hear your advice, critique, etc.
Below are images and a link to my repo attached.
Things I am unsure about:
How much should I care about impedance? What lines need to be tuned? Should I care at all? The fs of the clock is 3MHz.
Should the trace length be tuned? Or have I gone too far? The CLK and DATA lines are +/- 5mm equal length.
Did I miss obvious things?
Layer 2: GND
Layer 3: 1.8V DVDD
I have built several microphone arrays in the past, including a 64 microphone sphere. Place a series resistor on the clock outputs (22 or 33 ohms) near the chip driving the clocks. At four loads per clock you should have much issue. Just go from one to the next with a small a stub as possible. It is counter intutitve but the microphone closest to the clock source will have the longest delay and the worst signal because it will need to wait for the reflection to return. At a ps/foot this skew will be an irrelevency for audio signals.
You may also want a series resistor at each microphone data output, you can always make them zero ohm.
I have never been doing anything like that.
I don’t understand this circuit. Starting from top left. Do mic0 and mic1 have some integrated parameters telling one of them to not drive DAT0 while second drives it and then drive it while second not drives it. Or may be DAT0 is analog line allowing to get 4 states and read data from two sources at the same time?
After writing it…
I noticed LR pins are driven with different state. Is it something that allows them to work with the same CLK and DAT lines (like - long break in clock = reset and then one responds during first N clocks and second later).
Yeah according to the datasheet they recommend a 100 Ohm resistor to prevent ringing. So i just blindly copied their example design.
Regarding your comment about 4 loads per clock: I should have much issue? You mean that things will go bad like this? I don’t know why?
In the PCB layout i did match the length of the CLK and DATA lines up to +/- 5 mm. So i assume skew / async data is not a problem? Or did i fully over engineer this and I didnt need to do any form of length matching?
Thank you again for taking your time in reading my post and commenting on this, i truly appreciate it.
In terms of DATA out resistors, I did not see that in the recommendations in the IC documentations. However, you would recommend it? What would it solve?
Yeah, the microphones are configured as taking turns at driving the data line. Depending on driving LR HI or LO, it will determine when they write out the data, on CLK HI or CLK LO, so basically the data is fused over the data line.
Sorry, I mistyped. It was late and I was prepping my presentation for KiCon.
You should NOT have any issues with properly terminated net with up to 8 loads.
I have absolutely daisy chained the clocks up to 8 loads. I made sure to have minimal stubs.
If you don’t daisy chain, then instead use a star configuration for the clocks. In that case, I recommend one resistor for each clock signal. I often use a quad resistor pack for that purpose.
With a series terminated driver into a matched impedance trace, the wave first propagate down the trace at 1/2 the drive voltage. When it hits the end of the trace the reflection will come back causing the net to reach full voltage.
With that in mind, if you daisy chain the clock the closest microphone has to wait the longest time for the reflection. Hence the closest device actually has the worst propagation delay. I’ve done some huge busses on backplanes and you can clearly see a “flat spot” in the waveform during the delay. So long as that signal is continously increasing you are in the clear.
Again, the particular resistor value won’t matter much. Ideally if you use a 50Ohm trace and a typical output is has ~20-30 Ohms output impedance then a 33 ohm resistor will do the trick. If you use a 100 ohm trace then you may want a 68 ohm resistor. On many boards, I have simply chosen a convenient trace width and not controlled the impedance. I plop down a 33 ohm resistor and the check later with a scope. It works 99.9% of the time. If you over terminate with say a 100Ohm resistor then the flat spot will stay below the 1/2VCC switching point of the input and you’ll round the edges. At 3 MHz this shouldn’t be a problem. At 25 MHz+ I’d think hard about rounding off that edge.
Apologies, I reread the description of this projects category and you’re right. This is not the place for general PCB layout discussions and should be focused on Kicad related questions. I shall refrain from general EE questions. thank you.
I shall plonk down a 33 Ohm resistor and take a better look at my CLK and DATA traces, thank you for your time. And yeah, even the higher harmonics of a 3MHz square wave have wavelengths of >>5 meter so on this scale it all wouldnt matter.
