I have two project files. For one, the PCB layout is completed. I need to add schematic from another project file to the completed one. When I do it and after assigning the footprint, I update the PCB. But now the PCB is all messed up. Is there a way to update the PCB without affecting the existing layout?
explain in greater detail what you are doing, and what you mean with messed up.
I have one project file with the layout completed, lets call it A. I have to add some blocks to this project file from another project file, lets call it B. I copy and paste the required schematics from B to A. The footprints were assigned. Now I need to do the layout of the newly added block to the existing layout. But when I update the PCB, some components are updated like its
If you are doing what I think you are then you need to make sure that the references for the symbols in your schematic match the ones on the pcb. Then when doing the update pcb make sure the relink by references box is ticked.
I think you might be right, but I wonder what went wrong in the first place. AFAIK, the OP’s workflow should not have caused issues.
To be clear, if you go back to step one, with A’s layout complete, then the schematic’s symbols and the PCB’s footprints are linked via an invisible UUID. Pasting in new symbols from another schematic should create new instances, with unique reference designators. You’re free to re-annotate, or not. Then, running “Update PCB from schematic”, with “re-link” turned off, should leave all existing footprints untouched, and bring in all new footprints.
I agree, assigning matching ref designators and then running “re-link” is a good way to fix this. But I’m not sure how it got messed up in the first place.
Pasting additional circuit fragments into an existing one should be no different from entering it by hand in principle. Just make sure to do the usual ERC before updating the layout and it should just add footprints and ratsnest lines and not touch the existing layout. But if the schematic is not valid, e.g. duplicate refdes, no footprint assigned, etc. then you could get garbage.
Yes, true, but if the Re-Link footprints… is on and also re-annotation is set to re-annotate the whole schematic, you have introduced a big opportunity for *&^%$#@!.
This is not clear at all:
And this description seems to be an unfinished sentence:
Copy & paste between schematics from different projects normally does work, but it’s not clear where it goes wrong here. What data chaned? And what did it change into? It’s not needed to list all changes, as they probably all have the same root cause, but listing a few is helpful.