Ok, having one class for the whole network makes sense. But then there cannot be a direct connection between the width of the connection and the net class, there must be a certain transformation mechanism.
For example, I will create a class SEN50, which means Single Ended Non coplanar with a characteristic impedance of 50 Ohm. I cannot have a single value for the width, but it must be definable for the entire stackup, otherwise it may not be true that the entire net has an impedance of 50 Ohm. For current loads it is similar, the Curr1A class generally needs to be transformed to different thicknesses as the inner layers tend to have a different copper height than the outer.
yeah… but cant you do this ?
Still, the problem is that the router does not observe the rules in real time. If the rule is as below, you can still place a 0.2mm trace, when a 0.1 on layer 3 is all that is permitted. That’s no good. and it doesnt show the resolved rule clearance, either. so that needs to be a feature that goes in. Post DRC alert is no good because if the tool permits you to route a thousand tracks wrongly, that’s rework.
(rule "trace width by layer2"
(layer In1.Cu)
(condition " A.NetClass == 'HV' ")
(constraint track_width (min 0.3mm) (opt 0.3mm) (max 0.3mm))
(constraint clearance (min 0.15mm) (opt 0.15mm) (max 0.15mm)))
(rule "trace width by layer3"
(layer In2.Cu)
(condition " A.NetClass == 'HV' ")
(constraint track_width (min 0.1mm) (opt 0.1mm) (max 0.1mm))
(constraint clearance (min 0.1mm) (opt 0.1mm) (max 0.1mm)))
or
(rule "trace width by layer2"
(condition " A.NetClass == 'HV' && A.existsOnLayer('In1.Cu')")
(constraint track_width (min 0.3mm) (opt 0.3mm) (max 0.3mm))
(constraint clearance (min 0.15mm) (opt 0.15mm) (max 0.15mm)))
(rule "trace width by layer3"
(condition " A.NetClass == 'HV' && A.existsOnLayer('In2.Cu')")
(constraint track_width (min 0.1mm) (opt 0.1mm) (max 0.1mm))
(constraint clearance (min 0.1mm) (opt 0.1mm) (max 0.1mm)))
Yeah, so you write a DRC rule that says nets in net class XYZ have width A and clearance B when they’re on layer top or layer bottom. Then you write a rule that says when those nets are on layer 2 and layer 3, they have width C and clearance D.
The rules quoted by Glen are basically what you want.
The router does observe the rules in real time, but it will let you override them if you want (and then report it as a DRC error). One way that people often override the rules is with the “when routing from an existing track use its width instead of the current width setting” option, which would get you an undesired result in this case. If you turn it off, the router will use the opt trace width from rules on a per-layer basis.
but IMO ! and it should not permit you to override them without prompting you unless you explicitly say so.
At DRC time, that’s too late for 100 traces you routed with the wrong width.
In Altium if you try and place a trace outside the rules, a model dialog box pops up and asks you ’ do you really want to violate the rules for this object ’ ? Usually, you will say no
In the case of custom rules in Kicad, the tool should choose the opt constraint by itself if it knows. IE if I start placing a trace from say, a via with netclass xyzm then the opt trace should be chosen unless it picks up the trace width (per option) AND it satisfues the rules . This does not happen.
eh, if I put the tool into “sometimes override netclass settings” mode, I don’t want it to nag me when it sometimes overrides netclass settings.
This brings up some bad memories. A program I used 20+ years ago had this approach. In some situations I had to repair some 30+ track segments, and it asked for confirmation on each and every track segment, and that did get quite annoying after a while. (similar situations popped up several times).
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Hi Glen, Since you come here I am surprised how often you write about rules while I’ve never even tried to write a single rule 
OMG !
Hi Piotr.
Well, I’m a professional designer, with boards with many hundreds of parts, maybe a thousand, tens of thousands of traces, 6-12 layers. It’s too complex to have your brain do all the work…
If you dont have rules and fences and stop signs everywhere, the 0.5% of items that are wrong- the board will not work.
I know and I’m happy to see how you look at KiCad.
I am designing 2 layer boards. When I needed 3 layers I used 4 layer PCB and left one layer empty and send it to our contract manufacturer. He send it to PCB manufacturer who sent the same channel back the question if it is not a mistake and this layer I really want to have empty
I supposed that defining all rules (as you write 10+ pages) is more work/time than having them in mind while designing. I know this is a wrong assumption.
In Protel 3 (I used till 2017) at each PCB I divided footprints into footprint classes (small, medium, big) and for example defined rules to make Thermal Relief depending on class. But in KiCad I did it in footprint definitions.
I also had to use rules (based on IC reference) to delete Paste opening at its thermal pad to replace it with set of smaller openings. In KiCad I also have it done in footprint definitions.
So for me rules I was using became redundant after moving to KiCad
I practically need only a bigger clearance for tracks being ‘high voltage’ (24V is high for me) to make zones keeping bigger distance from them. One class with little higher clearance do the job but using more higher clearance (like for 4kV isolation) will not work, as KiCad understand it as clearance also between all nets in the class.
I designed PCB having such isolated part with KiCad V5. I don’t know if in V5 it was possible to use rules for it. What I know is that I didn’t used them.
May be if I will be designing something like this once more I will define a rule (I hope I will need only one rule ) or before it will happen may be clearance between classes will be available in KiCad to specify in a kind of table with all net classes listed there.
AFAIKT, the K8RC2 rule system, much expanded compared to 7, should meet most requirements, bugs aside.
By some good fortune the uploaded file contains most of the issues I’ve encountered using the differential routing tools. For those interested, the traces in question apply to J4 found on the bottom, left side of the pcb.
8-PortSwitch-d.zip (1.7 MB)
Some have offered suggestions that I should try kicad-8-rc2. I did. Basically unusable. No option 8 allowing trace length adjustment. The problems present in 7.10 are still there, so I’ll continue to use 7.10 for now.
Net SpWRxS4 with (9) says Tuned: Skew -0.0000 mm/0.0000 mm. This is an error as the Pad to Die difference between the +an - lines is 0.1295 mm. So apparently, at present Pad to die lengths are not included in any net length matching. I suppose that’s OK but you might have let the great unwashed know that that feature was not yet available. There might be a setting somewhere to turn that feature on, but I don’t know of it.
Overall, please note that the four pairs of J4 are all on the bottom with no vias and clean direct connection to the terminating pads.
SpWTxD4 is really perplexing. First note that its diagonal traces are shorter than those of SpWRxS4.
Summary: Routed length | Pad to Die | Full length | pad to die difference (absolute)
SpWRxS4+ 18.0962 5.0297 23.1260 0.1295
SpWRxS4+ 18.0962 4.9003 22.9965 0.1295
SpWTxD4- 17.6357 3.9029 21.5386 0.2318
SpWTxD4+ 17.6357 3.6711 21.3068 0.2318
So both visually and by measurement SpWRxS4 is longer that SpWTxD4. Setting the desired path length to 19.5000mm using (8) and the clicking on
SpWRxS4 I get Too short: 18.1978 mm
SpWTxD4 Too long: 21.5386 mm/19.5000mm , say what?
This is where I ran off the cliff…
Looking at the data, I discovered the Full length measurement of 21.5386, I’ve no idea where 18.1978 comes from.
Increasing the length goal to 23.25mm I get this.
Repeating the initial measurements:
SpWRxS4+ 23.1485 5.0297 28.1782 0.1294
SpWRxS4+ 23.1485 4.9003 28.0488 0.1294
SpWTxD4- 19.4417 3.9029 23.3446 0.2318
SpWTxD4+ 19.4417 3.6711 23.1128 0.2318
Sure is pretty, however the full length differences are much larger making everything much, much worse.
I think everyone would agree that at the end of any tuning exercise one would expect the full path lengths to match.
Everything else seems to be working great. Kudos on the inspection tools. Please do not release 8.0 until this is fixed.
Try 8.0.0~rc3, where single track/DP tuning separation was restored.
Your tracks are disconnected from pads by a couple of nanometers.
Basically press G or D on each track segment connected to a pad to fix it.
Select a pad or entire footprint and press U to check connectivity.
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that looks a bit better than your earlier posts.
Did accounting for the VIA delay improve the numbers? In your earlier post, you had not accounted for the via delay and you had pairs split with different numbers of vias (bad) .
I’ve found no problems at all with diff route matching, but my diff trace trombones are much more symmetrical than yours.
Ideally you need to have the same shapes.
this sort of thing will heavily mismatch the actual delay , and generate a dispersion line …
Your design will be sky-high with crosstalk and mismatched delays due to proximity and lack of coupling and assymetrical shapes .
I’m a bit puzzled by the assymetrical behaviour of the wiggles and will try and recreate it, the tool shouldnt let you do that unless you give it impossible geometry.
Differential length tuning wiggles should look like this ! note the symetrical shapes.
The tool will do that when the spacing (period of the meander) is set too low to allow for uniform curves on both sides of the pair
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@Flash_Packets set Minimum Spacing to something like 1mm
so it looks like this:
Note-when I set Minimum Spacing in Board Setup, it does not seem to control the placed meander.
I place a meander and then go into properties and then I can change it.
But that affects the length tuning ! so we have a problem ther ethat needs attention…
flash packets, I reviewed your design files
Let’s look at SpWTxD5
What you have there is a bit of a mess. There’s no way I’d expect the tool’s length tuning to work with what you’ve done. You have segments overlapping etc. clean it up - Suggest rip up that net and start from scratch. I have done that on your PCB…
I routed it using"Route Differential Pair" and the length was with 0.2mm matched in the pair. wow .
The PCB material wont be matched that well so that’s pretty damn good and I did not need to use the tuner !
It appears that the delay is mostly in the package so we need to put a single trombone in there at the sender (chip) end.
However, I gather you want to equalise all the traces going off board.
so, I will put an arbritrary diff meander line, had to hand set the Min Spacing to 1mm.
extended net another 3mm… OK, trace is still matched by 0.2mm , so far so good !
added another 5mm. trace still matched within 0.2mm. still works.
so, I think its wOK
I think your technique is causing the tool to have trouble. No tool would work with the methods you used.
I know this is one of your first high speed designs because the original file set you posted demonstrated this, It’s good you took on some of the suggestions.,
With Diff pairs, the pair has to be coupled in phase, cant be a bit here and a bit there.
Pick up a copy of High Speed Design by Howard Johnson.
see the nice trombone I put in ? I could have spaced the traces, tightened up the coupling, and put it elsewhere. Try spacing the traces tighter together- your diff traces are miles apart , they would be better to be 0.1 or 0.125 apart. then you would fit alot more in.
yes I could clean up the pad entry a bit on the connector.
before it was like this :
The tools appear to work well. Sorry I could not replicate your problems after I cleaned up the traces.
Others might try though, I will leave it at this.
Oh and Ritchey is talking about what traces are routed that are about as spaced as they are tall in copper. Your traces have trucks between them, if you tighten that up, you’ll get more room for the meander lines.
Also, beware of overlapping length tuning sections, I found a few segments in your file that had more than one length tuning sections, - that is to say, overlapping - all but one inactive in the region . That might cause an issue.
It is likely the tuning / length calc tool is not robust in these difficult unclean layout cases.
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