One board is about 25 mm x 24 mm with three ICs, seven passives, four connectors, one “pad-only” connector, and one screw hole. It’s mostly routed using two layers, but routing is NOT my forte. Some connector locations are fixed by the mating component.
The other board has a known schematic and I’ve started the layout but that’s all (no routing done). It would likely end up being about 32 mm x 20 mm. It has three ICs, eight passives, four FETs, three connectors, one “pad-only” connector. This board no mounting holes. One of the ICs (LTM8040) is a PGA with 77 potential pins (66 actual) but many are common so there are ‘only’ nine (9) distinct signals. The connectors can be moved but must stay on the back of the board with the wire entries facing outward.
All components not in the KiCAD 6.05 libraries have footprints and 3D models. These are KiCAD v6 (.0.5) projects. Two layers are preferred, but four is acceptable.
Completion before September 2022 is desired.
Please PM me for details if you have any interest in either or both.
I searched for similar topics but I found nothing very current.
When routing gets dense, the first thing that suffers is the GND plane, which reduces EMI immunity and increases EMI radiation, and how much of that is “acceptable” can be difficult to estimate. The design rules also matter a lot. Narrower tracks and clearances obviously lets you cram more of them in a tight area but the PCB gets more expensive to produce. Smaller features are sometimes (often?) also only supported for 4 or more layer boards.
For the FET’s, current handling and dissipation have to fit with track width and amount of copper.
I can have a look at it if you’re willing to send (PM?) me the project, but the only promise I’ll make is that I’ll have a serious try to get id done and an answer within a few days.
US only: I don’t understand laws elsewhere. It’s a simple transaction, but I don’t want to get caught with some EU rule I don’t know about. It’s not prejudice, just practical.
Currents are modest, less than 1A on the LMT8040 board. Less than 10 ma on the other. The FETs will be pretty cool given the currents and RDS-ON values.
Density: the boards can be larger if needed although there is a ‘Y’ axis limit on the first one.
The first board is working well on a prototype board.
The second is only partially prototyped and is therefore only partially working. The prototype should be completed by Monday.
I will package the first project by Monday at the latest. They will include the project-specific parts footprint / 3D model libraries.
Meh, I don’t even want money for the job.
Just a comparably suitable donation to the KiCad project itself.
Sometimes I do these projects for fun and to help beginners. Routing is better then sudoku.
Here a thread from a beginner with KiCad that I helped along a bit with his project:
At the moment I’m guessing, Small PCB, two handfuls of parts, maybe half a day of work, or a day if it gets real dense. What’s that worth?
I apologize for the delay. My recollection about the state of the projects was bad. They were 5.x and one used a symbol from SnapEDA. I am trying to rebuild them now. I’m not particularly facile with symbol/package/model conversions.
I understand. I’ll take a different path.
To others who expressed interest privately, thank you.