Looking for Practical USB C Connector

mykepredko · June 18, 2024, 9:07pm

Hey Folks,

I’m designing a board with KiCad that uses a USB C connector. My basic requirements for the part are:

16pin 8 dummy
SMT Pads with solder lugs. I want to avoid passing signals between sides/planes - keep everything on the top
Not a mid-mount USB C connector as I want manufacturing to be as cheap as possible and I have PTH parts which means a wave and I don’t want to get into custom wave soldering fixtures
Pre-existing and usable KiCad library files (Currently using Ultra Librarian)
Available at Digi-Key and LCSC (Hopefully with LCSC having a great price)

After much searching, I’m using the Amphenol 10155435-00011LF at Digi-Key

Which is okay but throws a ton of DRC errors:

[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(137.4948 mm, 151.8852 mm): Polygon on F.Cu
    @(137.6726 mm, 152.4567 mm): Pad A1 [Earth] of J9 on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(137.4948 mm, 151.8852 mm): Polygon on F.Cu
    @(137.9266 mm, 152.4567 mm): Pad B12 [Earth] of J9 on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
    @(138.4727 mm, 152.4567 mm): Pad A4 [VBUS] of J9 on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
    @(138.7267 mm, 152.4567 mm): Pad B9 [VBUS] of J9 on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(143.0955 mm, 151.8852 mm): Polygon on F.Cu
    @(143.5273 mm, 152.4567 mm): Pad A9 [VBUS] of J9 on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(143.0955 mm, 151.8852 mm): Polygon on F.Cu
    @(143.2733 mm, 152.4567 mm): Pad B4 [VBUS] of J9 on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(143.8956 mm, 151.8852 mm): Polygon on F.Cu
    @(144.3274 mm, 152.4567 mm): Pad A12 [Earth] of J9 on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(143.8956 mm, 151.8852 mm): Polygon on F.Cu
    @(144.0734 mm, 152.4567 mm): Pad B1 [Earth] of J9 on F.Cu
[starved_thermal]: Thermal relief connection to zone incomplete (layer F.Cu; zone min spoke count 2; actual 1)
    Local override; error
    @(78.7500 mm, 108.2500 mm): Zone [Earth] on F.Cu
    @(78.1500 mm, 108.2012 mm): Pad 2 [Earth] of C1 on F.Cu
[invalid_outline]: Board has malformed outline (not a closed shape)
    Local override; error
    @(136.6801 mm, 153.5679 mm): Segment on Edge.Cuts
[invalid_outline]: Board has malformed outline (not a closed shape)
    Local override; error
    @(136.6801 mm, 157.5954 mm): Segment on Edge.Cuts
[invalid_outline]: Board has malformed outline (not a closed shape)
    Local override; error
    @(145.3199 mm, 153.5679 mm): Segment on Edge.Cuts
[invalid_outline]: Board has malformed outline (not a closed shape)
    Local override; error
    @(145.3199 mm, 157.5954 mm): Segment on Edge.Cuts
[holes_co_located]: Drilled holes co-located
    Local override; warning
    @(114.5000 mm, 86.7500 mm): Via [Vdrive] on F.Cu - B.Cu
    @(114.5000 mm, 86.7500 mm): Via [Vdrive] on F.Cu - B.Cu
[copper_edge_clearance]: Board edge clearance violation (board setup constraints edge clearance 0.5000 mm; actual 0.0000 mm)
    Rule: board setup constraints edge; error
    @(136.6801 mm, 153.5679 mm): Segment on Edge.Cuts
    @(136.6801 mm, 153.0219 mm): Pad 19 [<no net>] of J9 on F.Cu
[copper_edge_clearance]: Board edge clearance violation (board setup constraints edge clearance 0.5000 mm; actual 0.0000 mm)
    Rule: board setup constraints edge; error
    @(145.3199 mm, 153.5679 mm): Segment on Edge.Cuts
    @(145.3199 mm, 153.0219 mm): Pad 20 [<no net>] of J9 on F.Cu
[copper_edge_clearance]: Board edge clearance violation (board setup constraints edge clearance 0.5000 mm; actual 0.0000 mm)
    Rule: board setup constraints edge; error
    @(136.6801 mm, 157.5954 mm): Segment on Edge.Cuts
    @(136.6801 mm, 157.2017 mm): Pad 21 [<no net>] of J9 on F.Cu
[copper_edge_clearance]: Board edge clearance violation (board setup constraints edge clearance 0.5000 mm; actual 0.0000 mm)
    Rule: board setup constraints edge; error
    @(145.3199 mm, 157.5954 mm): Segment on Edge.Cuts
    @(145.3199 mm, 157.2017 mm): Pad 22 [<no net>] of J9 on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(130.9257 mm, 87.8243 mm): Track [Vdrive] on F.Cu, length 1.5193 mm
    @(130.5000 mm, 85.2500 mm): Track [Net-(U9-BRA)] on F.Cu, length 4.5000 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(130.9257 mm, 90.5743 mm): Track [Vdrive] on F.Cu, length 2.7500 mm
    @(130.5000 mm, 85.2500 mm): Track [Net-(U9-BRA)] on F.Cu, length 4.5000 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(144.0528 mm, 152.4567 mm): Track [Earth] on F.Cu, length 0.3072 mm
    @(143.8956 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(144.3600 mm, 152.4567 mm): Track [Earth] on F.Cu, length 1.0967 mm
    @(143.8956 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(108.4257 mm, 87.5743 mm): Track [Vdrive] on F.Cu, length 1.1657 mm
    @(108.0000 mm, 85.2500 mm): Track [Net-(U8-BRA)] on F.Cu, length 4.5000 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(108.4257 mm, 90.5743 mm): Track [Vdrive] on F.Cu, length 3.0000 mm
    @(108.0000 mm, 85.2500 mm): Track [Net-(U8-BRA)] on F.Cu, length 4.5000 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(85.9257 mm, 87.8243 mm): Track [Vdrive] on F.Cu, length 1.5193 mm
    @(85.5000 mm, 85.2500 mm): Track [Net-(U7-BRA)] on F.Cu, length 4.5000 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(85.9257 mm, 90.5743 mm): Track [Vdrive] on F.Cu, length 2.7500 mm
    @(85.5000 mm, 85.2500 mm): Track [Net-(U7-BRA)] on F.Cu, length 4.5000 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(137.9522 mm, 152.4426 mm): Track [Earth] on F.Cu, length 0.3048 mm
    @(137.4948 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(137.6474 mm, 152.4567 mm): Track [Earth] on F.Cu, length 0.3048 mm
    @(137.4948 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(137.9522 mm, 151.0478 mm): Track [Earth] on F.Cu, length 1.4089 mm
    @(137.4948 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(130.5000 mm, 89.7500 mm): Track [Net-(U9-BRA)] on F.Cu, length 0.1051 mm
    @(130.9257 mm, 90.5743 mm): Track [Vdrive] on F.Cu, length 2.7500 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(143.5450 mm, 152.4567 mm): Track [VBUS] on F.Cu, length 0.3023 mm
    @(143.0955 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(138.4425 mm, 152.4567 mm): Track [VBUS] on F.Cu, length 0.3075 mm
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(108.0000 mm, 89.7500 mm): Track [Net-(U8-BRA)] on F.Cu, length 0.1051 mm
    @(108.4257 mm, 90.5743 mm): Track [Vdrive] on F.Cu, length 3.0000 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(138.7500 mm, 152.4567 mm): Track [VBUS] on F.Cu, length 3.8067 mm
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0757 mm)
    Rule: netclass 'Default'; error
    @(85.5000 mm, 89.7500 mm): Track [Net-(U7-BRA)] on F.Cu, length 0.1051 mm
    @(85.9257 mm, 90.5743 mm): Track [Vdrive] on F.Cu, length 2.7500 mm
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0772 mm)
    Rule: netclass 'Default'; error
    @(138.7500 mm, 153.2054 mm): Track [VBUS] on F.Cu, length 0.0569 mm
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(138.7500 mm, 152.4567 mm): Track [VBUS] on F.Cu, length 0.7487 mm
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.1174 mm)
    Rule: netclass 'Default'; error
    @(138.7902 mm, 153.2456 mm): Track [VBUS] on F.Cu, length 0.9642 mm
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(143.2428 mm, 152.4567 mm): Track [VBUS] on F.Cu, length 0.8005 mm
    @(143.0955 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(70.0000 mm, 91.5500 mm): Pad 5 [Net-(CR17-Pad3)] of Q1 on F.Cu
    @(70.4318 mm, 91.4074 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(70.0000 mm, 92.2000 mm): Pad 6 [Net-(CR17-Pad3)] of Q1 on F.Cu
    @(70.4318 mm, 91.4074 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(70.0000 mm, 92.8500 mm): Pad 7 [Net-(CR17-Pad3)] of Q1 on F.Cu
    @(70.4318 mm, 91.4074 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(70.0000 mm, 93.5000 mm): Pad 8 [Net-(CR17-Pad3)] of Q1 on F.Cu
    @(70.4318 mm, 91.4074 mm): Polygon on F.Cu
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(136.6801 mm, 153.0219 mm): Pad 19 [<no net>] of J9 on F.Cu
    @(136.6801 mm, 152.4758 mm): NPTH pad of J9
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(136.6801 mm, 153.0219 mm): Pad 19 [<no net>] of J9 on F.Cu
    @(136.6801 mm, 153.5679 mm): NPTH pad of J9
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(145.3199 mm, 153.0219 mm): Pad 20 [<no net>] of J9 on F.Cu
    @(145.3199 mm, 153.5679 mm): NPTH pad of J9
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(145.3199 mm, 153.0219 mm): Pad 20 [<no net>] of J9 on F.Cu
    @(145.3199 mm, 152.4758 mm): NPTH pad of J9
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(136.6801 mm, 157.2017 mm): Pad 21 [<no net>] of J9 on F.Cu
    @(136.6801 mm, 157.5954 mm): NPTH pad of J9
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(136.6801 mm, 157.2017 mm): Pad 21 [<no net>] of J9 on F.Cu
    @(136.6801 mm, 156.8080 mm): NPTH pad of J9
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(145.3199 mm, 157.2017 mm): Pad 22 [<no net>] of J9 on F.Cu
    @(145.3199 mm, 156.8080 mm): NPTH pad of J9
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)
    Rule: board setup constraints hole; error
    @(145.3199 mm, 157.2017 mm): Pad 22 [<no net>] of J9 on F.Cu
    @(145.3199 mm, 157.5954 mm): NPTH pad of J9
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(137.6726 mm, 152.4567 mm): Pad A1 [Earth] of J9 on F.Cu
    @(137.4948 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(138.4727 mm, 152.4567 mm): Pad A4 [VBUS] of J9 on F.Cu
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(143.5273 mm, 152.4567 mm): Pad A9 [VBUS] of J9 on F.Cu
    @(143.0955 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(144.3274 mm, 152.4567 mm): Pad A12 [Earth] of J9 on F.Cu
    @(143.8956 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(144.0734 mm, 152.4567 mm): Pad B1 [Earth] of J9 on F.Cu
    @(143.8956 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(143.2733 mm, 152.4567 mm): Pad B4 [VBUS] of J9 on F.Cu
    @(143.0955 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(138.7267 mm, 152.4567 mm): Pad B9 [VBUS] of J9 on F.Cu
    @(138.2949 mm, 151.8852 mm): Polygon on F.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.1200 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; error
    @(137.9266 mm, 152.4567 mm): Pad B12 [Earth] of J9 on F.Cu
    @(137.4948 mm, 151.8852 mm): Polygon on F.Cu

I can ignore them, but I’m uncomfortable doing that because a) they might be indicating a real problem when I send the board out for fab and b) there may be an unrelated error stuck somewhere in there that I miss scanning over them.

Can anybody recommend a part that meets my requirements above? I would work with an LCSC only solution.

I don’t feel like I’m asking for the moon but I’ve spent many hours on this with surprisingly little luck.

This is my first post, so please be kind.

Thanx!

paulvdh · June 18, 2024, 9:36pm

Connectors are always a bit problematic. There can be hundreds of different “USB-C” connectors with different footprints. Sites like SnapEDA and PCB Libraries have many footprints (a million or more), but such sites generally have their own database format, and output is generated from scripts. It’s quite normal such footprints need a bit of tinkering to fix some details.

KiCad has a quite good editor for footprints. Personally I find this more important then big libraries. There will always be footprints that are not available anywhere, and with the editor you can make them yourself. And it does not take “many hours” to design a (simple) footprint. Simple footprints can be designed in 10 minutes or so. Gathering the data, and verifying afterwards the footprint is correct takes more time then the drawing itself.

From your listing I see lots of violations between pads and Polygons. Normally there should not even be polygons on a copper layer. I assume these polygons exist because of the non-native origin of this footprint.

I (and probably others too) are willing to have a look at it, You can make it easier by putting the footprint in a small test project and post it here. This also ensures both parties are discussing the same footprint.

mykepredko · June 19, 2024, 12:42am

HiPaul,

I realize that about footprint editors - but as this is my first experience with KiCAD (although not my first with PCB CAD tools) I wanted to minimize the amount of time I spent in the weeds and not actually getting a board together. I’ve tried my hand at one already for a simple standoff (and I’ll probably put that up for a question later.

Here is my simple board (after running DRC) which passes the power and data signals of the USB C connector to a JST XH connector. The two 0.11Ω resistors are for any connecting board to recognize that the connector is present. It’s a two sided PCB with the backside being a copper flood for Ground (“Earth”).

I hope that this is acceptable for your uses.

Here is the project:
USBC_KiCAD.zip (437.4 KB)

When I was doing my board, I was able to get the power/ground pins to link to the appropriate nets, but not in this case - if this is a problem let me know and I’ll see if I can figure out how I did them in the past.

Thanx for your help.

paulvdh · June 19, 2024, 4:23am

It’s a bit of a mess

Files and Names.

First thing I noticed are the filenames in your project. It’s clear you’re still struggling a bit with starting with KiCad.

When uploading (or archiving) your project, you don’t have to include the "USBC_KiCAD-backups** directory. This directory currenly has 6 backups of your project. If KiCad ever crashes, or you do something silly yourself, you can look into these zip files for an older version.
There are lock files in your project. (Starting with a tilde, and with extension .lck. This is likely an indication KiCad has crashed for you. Normally KiCad cleans these file up themself. When these files are present when the project is closed, you can always delete them.
The infamous fp-info-cache file. It’s a “big” file (3.3MiB) and a bit of a silly KiCad quirk. It is just a cache file for the library system, and it’s not important. KiCad can re-generate this file (within a few seconds) when it’s missing. Some day it will be moved to somewhere else…
The included libraries… Those need some organization, but it’s not really important at the moment.

Schematic

You are using an “Earth” symbol. This is bad practice. “Earth” has a special meaning, normally “GND” is used, which is a “local reference”. Although it’s not very important at the moment, I replaced them anyway.

Your (downloaded) symbol for your connector is… one of the ugliest I’ve seen

It’s typically such a “minimal effort” symbol from one of those big library vendor sites.

My own experience with USB-C is very limited, but as far as I know, pin names are standardized. A1 though A12 and B1 though B12. And https://en.wikipedia.org/wiki/USB-C confirms this. KiCad uses the pin numbers (i.e. “A1” is a pin number). for matching pins of symbols to pads on the PCB. Because of this standardization, you can very likely just use one of the symbols from KiCad’s default libraries for your USB connector.

So I took: USB_C_Receptacle_USB2.0_16P from KiCad’s default library. Just look at the difference:

There are a few important thing here:

Because of the many different USB-C wiring possibilities, you must use a connector that has all the pins you are interested in.
KiCad makes use of Pin Stacking to reduce the clutter on the schematic. Both the cyan GND pin and the VBUS pins are multiple pins stacked on each other. You connect one in the schematic, and all on the PCB have to be connected to match. You can look up more details in the manual.

With KiCad’s highlighting function (Backtick key) I checked the pins you are using. Both A7 and B7 are DNx or D- in KiCad’s own library. Similar for the other used pins.

Next is the footprint link. I Just copied it from the ugly symbol to KiCad’s native symbol.

To make sure I don’t make a mistake, I place local labels on connector J1.
The other pins also seem all right, so after a bit of cleanup the schematic now looks like:

I’ll leave those resistors and the other connector for you to decide what to do with it.
My own preference is to use as much as KiCad’s native symbols as possible. I find KiCad’s native libraries better in quality then libraries from other sources. KiCad’s own libraries are controlled pretty strictly by the KLC (KiCad Library Convention)

Next step is: Schematic Editor / Tools / Update PCB from Schematic [F8]. I use Options / Re-link footprints to schematic symbols based on their reference designators to re-create the connection between the schematic symbol I replaced, with the footprint that is already on the PCB.

Note there are warnings about missing pads (19 though 21) and the S1 pad. That is the next step.

PCB

On the PCB, you can see that the labels I added have named the nets on the PCB:

… but it’s still the old footprint with all the errors in it.

Your footprint has a bunch of issues.
I loaded it directly from the PCB into the footprint editor (With [Ctrl + e]) and the most obvious errors are:

Coordinates of pads are “weird numbers” both in metric, and in banana units.
There are graphical polygons over some of the (combined) pads.
The shield pins are a mishmash of both drilled holes (And NPTH too!) and a line on Edge.Cuts. That is something that can never work. This will very likely result in your PCB being rejected by your PCB manufacturer. (Or they spend time fixing it themselves).

30, Coordinates. Hmm, I’ll see what I can do, but no guarantees about correctness.
Your footprint has:

Pads with a size of 12 by 45mils.
0.5005mm pitch between the pads.

That is a bit of a mess. I’m not going to fix that.

31, Graphical Polygons

I placed copies of other pads on top of the “combined pads”. (only visually aligned, tolerance approx 10um).
Renumbered the copied pads to the correct pin numbers.
Removed the graphical polygons.
Deleted the very small square pads.

32, The slotted THT pads for the shield

Renumbered pads 19 though 22 all to S1. This is the same as the schematic symbol. In KiCad it is common to have multiple pads with the same pad number in a footprint. KiCad interprets this such that all these pads have to be connected by copper.
Deleted the NPTH holes (all 8 of them).
Deleted the thick (0.6096mm wide, 1.0922mm long) lines on the Edge.Cuts layer. (4x).
Changed one of the pads:
- SMT → THT.
- Hole set to oval.
- Width: 0.6mm, length guessed at 0.7mm.
Right click, and Copy Pad Properties to Default.
Select other three “shield” pads, right click and Paste Default pad Properties to Selected.

Then I closed the footprint editor. KiCad then prompts me what to do, and I had KiCad replace the footprint on the PCB with the modified version.

Update PCB from Schematic [F8]

Pad numbers of the footprint have changed, so to update the netlist, we do the Update PCB from Schematic [F8] again. At this point it is important that the Replace footprints with those specified in the schematic is OFF. If this option is on, then the footprint I just modified will be replaced with the default version in the library. To fix it completely, you also have to do some library management, and export the modified footprint to the location where the schematic expects it to be. In KiCad the schematic, and it’s attributes is always the “origin” of all data.

The rest of the tracks can now be routed.

DRC

DRC still gives a whole lot of errors. There are a lot of violations with:

The cause for this error is that the footprint only has gaps of 0.1916mm between the pads, while the board setup has specified that no clearances smaller then 200um are allowed. 0.2mm is already quite narrow. To fix it, I go to PCB Editor / File / Board Setup / Design Rules / Net Classes and I change the clearance for the Default netclass from 200um to 190um. You should check with your PCB manufacturer if this can be manufactured reliably.

Now there are 4 DRC errors left. All these are for the NPTH in your footprint. They are too close to the SMT pads.

There are different ways to handle this.

Change the pads a bit.
Ignore it yourself (Not recommended, it obscures other errors if you leave it the DRC window.)
Disable this violation (Try right clicking on the text in the DRC window).

There are also still a few warnings:

Warning: Silkscreen clipped by board Edge Seems logical. Silkscreen should not be printed outside of the PCB. Either move the footprint inward, or remove these silkscreen lines in the footprint itself.
Warning: Silkscreen clipped by solder mask Seems self explanatory.
Warning: Footprint’1015 bla bla’ does not match copy in library “101 bla bla”. This is because I modified the footprint, but have not put it in a library. This is a pretty important step. If you don’t put your footprints back in a library, then it’s all too easy to loose your modifications because your footprint can be overwritten by the library default footprint. Library management is another topic and I’ll lave it to you what to do with this.

Zip up and post the project.

It’s a bit smaller now, because I did not include all the duplicate and nonsense info. I still left all the libraries you added. As I wrote earlier, library management is a separate topic.

2024-06-19_USBC_KiCAD.zip (30.5 KB)

The End

All this took me a bit more time then anticipated. Most of the effort was in writing it all down, and re-checking that I what I wrote down makes sense. The easy way out for you is to use this modified footprint, but you don’t learn much from that. I suggest you first have a look at the modified project I uploaded, and then re-create the steps I did in your own faulty project. Or maybe re-visit it later, when you think you’re ready to learn some things about footprint creation and modification.

mykepredko · June 19, 2024, 5:08am

Hi Paul,

Wow. Thank you for this it’s a) really appreciated and b) somewhat overwhelming in breadth.

There’s a lot to process here before I can give you a comprehensive/intelligent reply - I’m going to need a half day or so to go through this reply, look at your updated project and cogitate on what is the best way to proceed.

As for passing the “project”, you can see that I simply took the folder that the project was in and .zipped it. In the future, what is expected when somebody is asking to share it?

Thanx again - this is really appreciated.

myke

svgeesus · June 19, 2024, 2:42pm

Nice tutorial! Hope it gets linked from somewhere, I happened across this topic by chance.

mykepredko · June 19, 2024, 10:04pm

Hi Dave,

Thank you again for all your hard work - it was very, very helpful.

As for the mini project, I trimmed the outside four pads, corrected the part of edge error along with the silkscreen warnsings and when I run DRC:

I’m implementing this on my main PCB.

Thanx again!

myke

mattyclark1981 · June 21, 2024, 1:16pm

I’ve done a couple of designs with USB 2.0 over type C, for an STM32 processor.

I’ve used both a GCT USB4085 (all thru hole, horizontal) and USB4145 (thru hole stakes, but SMT pads, vertical), and I have to say the thru hole part is much easier to lay out. Soldering isn’t too dificult either.

The problem with the USB4145 is that the pins aren’t in a sensible location to allow connection on one side of the board, so you end up adding vias, by which time, you might as well go for a through hole design. It’s neater, and a more symmetric solution. Not sure if this is just a GCT thing or whether all SMT USB type Cs have similar issues. More investigation is required.

Heres the USB4085. Note the neat crisscrossing of the D+ and D- lines in the middle:

Here’s the USB4145. Looks horrible, and might well move away from GCT for this design, as they don’t seem to have a vertical all thru-hole part in their line-up.

mykepredko · June 21, 2024, 4:38pm

Hiya,

Thank you for the suggestions. This is for an STM32G0B1 board.

I originally went with a PTH part (the Amphenol GSB1C211110DS1HR) and got presented with an overwhelming number of errors with the available footprint so I started working through the SMT/PTH parts.

I didn’t look at parts with SMT signal pins that were in two tiers, like you’ve shown in your lower image - it seemed to me that it would be unnecessarily complex when there were parts with easier to work with footprints available.

Just for background, I’m an experienced EE and PCB designer (previously used Cadence) with a number of micro USB interfaces behind me. I probably approached doing my first design on KiCAD, with the wealth of available part libraries, a bit arrogantly thinking I could get away without any footprint development (the most tedious part of laying out a PCB) and without really understanding the options available within the KiCAD part libraries.

If it weren’t for the USB C connector and one other part that, I knew going in, would have to have its footprint built, this project would have been entirely hiccup free.

Cheers!

mattyclark1981 · June 21, 2024, 5:16pm

The lower image is a vertical mount part, stuck (relatively speaking) in the middle of the board. GCT have decided to bring the ‘A’ pins out one one side and the ‘B’ pins on the other.

The connector will poke through the case for an ouside world connection. The project as a whole is a e-ink sign for my office door. 7" e-ink display, lithium battery, and a wi-fi interface for control. The USB is really just for bootloadering and charging the battery, and I’m only going with Type C, because the battery charge controller I’m using has the ability to have 3 programmed levels for charging - 100mA, 500mA or whatever you like up to 1.5 amps, so I can use the newer high powered chargers properly.

I’ve been looking around on Mouser, Digikey, Farnell and so on, trying to locate a vertical mount that has through hole pins, or a sensible SMT pin arrangement, but no luck so far.

I’m sure it’ll work, but from a length / impedance matching perspective, I’d prefer to have a more symmetrical routing for the D+ and D- traces. Maybe I’m worrying about nothing…

Marv · June 21, 2024, 6:37pm

I might add, while not so critical for USB 2.0, it isn’t a bad idea to follow layout guidelines for USB traces. Ideally, the D- and D+ should be routed as a differential pair.

Good luck with your project!

mykepredko · June 21, 2024, 6:43pm

That was done right from the start - but always good to remind people that USB D+/D- are actually a differential pair.

Thanx!

Evan_Shultz · June 24, 2024, 1:24pm

I discovered Molex 2171790001 (https://www.digikey.com/en/products/detail/molex/2171790001/13913749), which is rather smaller than many other USB-C 16-pin connectors. There are Taiwanese and Chinese crosses for it, but the 6.5mm depth made it stand out from other connectors if space is an issue.

mykepredko · June 24, 2024, 2:42pm

Thank you for following up with this.

I did look at this part but the Ultra Librarian model has problems with KiCAD.

With what I know now, I would have designed my own footprint or scoured the basic parts better (ie maybe there is a good Global Library footprint for this part).

I finished the PCB over the weekend:

And I’m reasonably pleased with the way it came out.

Again, thank you for making the suggestion - it’s really appreciated.

mattyclark1981 · July 11, 2024, 3:37pm

Just a little bit of an update. I decided to stick with GCT for my project, and received PCBs yesterday.

I’ve done a quick test with one of the boards, and a GCT USB4145 connector, and I was pleasantly suprised how easy it was.

The shell stakes do a lot to help with alignment, so the part is held in the right place. No solder bridges other faults I could find buzzing out with the multimeter.

As I didn’t put paste apertures in for the shell stake holes, I do have to solder these manually after reflowing, so I need to update this on my footprint.

Picture attached of one side.

system · October 9, 2024, 3:37pm

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