Local Clearance for traces entering TQFP package

Sorry if this is a repost.

Trying to layout an 80-TQFP package, but I’d prefer my track-to-track clearance to be 10mil except going to the TQFP, which seems to need a clearance of 8mil to allow the traces to dock with the pads.

Is there a sensible way to do this, or should I just change my global clearance to 8mil and be done with it?

Thanks in advance,


Changing clearance on the fly would be … complicated in KiCad.
In KiCad the pads get the same clearance as the netclass to which the pads belong, and if you make it too big you get DRC errors for the pads in the footprint. To prevent this you would need to use net-ties on each pin, and then you will still have trouble to find room on your PCB.

You may get a small advantage of specifying width and clearance in metric, as QFP’s are metric, but overall the difference would be negligible small.

Do you have a specific reason for wanting 10mil clearance, or is it just a habit? I think that even bog standard PCB fabs reliably produce PCB’s with 5 mil clearance in their “standard” process. 4 layer boards can often have even smaller production parameters.

Just had a peek at:
and they suggest a minimum track width of 6mil for their standard process, but no mention of clearance.

In the upcoming KiCad V6 (I have not used the nightlies myself yet) there is apparently a system to suppress specific DRC errors. That may be usable to suppress the pad to pad DRC errors if you set the clearance to 10mil.

Nope, no reason, just pure habit. Our older boards are 10mil traces with 10mil clearance.

I’m very new to PCB layout. Can I reduce the clearance on my copper pours to 8mil as well, or is that better left larger?



Some board manufacturers specify a bit larger clearances for copper zones, others don’t. So there seems to be some advantage of keeping this clearance a bit bigger.

But as I suggested before. PCB production has advanced in the last 20+ years or so. PCB’s have not only become cheaper (in low quantities) but also can be made with smaller features.

Instead of asking on this forum, you would be better off with looking at the website of your PCB manufacturer. (Or compare a bunch of them) and then devise what you think are sensible design rules for you.

https://www.pcbway.com/ has an easy way to get links to a bunch of PCB factories (and their websites) which you can use to compare their recommendations for design rules.

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There’s a better system in 5.99 (in the future 6.0), the new DRC rules system where you should be able to change the rules locally around the footprint. See Need some guinea pigs for a rule-based DRC <<PROTOTYPE>>. I’m not sure if this specific feature is yet ready, but it was of the known use cases for the system when it was planned.

Thanks! I’ll do some more research. Much appreciated.

Would that also solve the issue of traces not ‘docking’ onto the pads when I try and route them, or just prevent issues when running the DRC?



AFAIK the rule system isn’t “hooked” into the push’n’shove router yet in the nightly builds but is intended to be before v6.0. This means that it should allow routing with smaller clearance to the pads automatically.

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80 pin pqfp is an easy job for the low cost PCB Fabs to etch, but at the limit of my hand soldering

Set your clearance to 8mil and be done with it. That’s an easy resolution for any modern board house, no reason to make your life complicated for 10mil.

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The new rules system is now hooked in to PNS. So if you find bugs/shortcomings, please report them.

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