I just used the tune track length tool of KiCad and realized that vias are not taken into account for the total tracklength. Is this as it should be or is it a bug?
To test it I placed 10 vias on a track and it gave the length of 11.315 mm.
I then routed the exact same track, but without the vias and it gives a length of 11.315 mm as well.
Wouldn’t it be a good approach to take the board thickness as the vias thickness ? After all, the difference in most cases would be below a millimeter.
p.s. The PCB thickness value, influences the thickness of the board’s 3d model generated by StepUp
As the board stackup is available in 5.99 it should be a straitforward task to add the appropriate length between the respective layers when a via is present in the measured track.
Does someone know if this is planned?
The board thickness is only an approximation in the case when the via takes the track from front to back or back to front. If the board has 4 or more layers, the approximation will be quite poor for vias between a surface layer and the inner layers.
Yes, thank you. That is what I have been trying to do, but unfortunately in some cases they are unavoidable. That is why I wanted to take the via lengths into account and was surprised that they weren’t.
This is good to know. I would not have expected it to work like this. Is it measuring trace length from the edge of the annular ring on the via? So if you change the size of the annular ring on the via, will it measure a different trace length?
I will try this with Altium. I have only used length for differential tuning so absolute length was not important at the time.
Hi feralbeagle! First post right here. I’m working on my third board prototype on Kicad which has a microSD 4-bit bus and I intend to run it as close to full speed (50MHz) as possible. I am of course tuning track lengths.
Regarding your question I don’t think Kicad accounts for the physical shape and dimensions of the vias, it clearly seems to me it reads the lines on both sides of the board as if they were on the same plane and the via being solely a bidimensional point where the tracks meet. So I am pretty sure there is not much worry about the annular ring size in Kicad.
If you care to, check out application note AN4661 by ST Microelectronics (for F7 series, I’m using F746VGT6). On page 45 there is a point calling for keeping the same amount of vias in all SDMMC data bus lines which (in my humble opinion) suggests it might be a common practice for length matching in ~50MHz application layout.
This seems to be a good workaround for two layer boards if you are willing to sacrifice speed should the parasitics of the vias degrade the signals too much (my case).
A 1.6mm via is hardly significant at 50 MHz where the wavelength is around 4m on a PCB. So long as you only have a few vias you can ignore them.
The impedance discontinuity at GHz frequencies is more of a problem than the via length
