Hi feralbeagle! First post right here. I’m working on my third board prototype on Kicad which has a microSD 4-bit bus and I intend to run it as close to full speed (50MHz) as possible. I am of course tuning track lengths.
Regarding your question I don’t think Kicad accounts for the physical shape and dimensions of the vias, it clearly seems to me it reads the lines on both sides of the board as if they were on the same plane and the via being solely a bidimensional point where the tracks meet. So I am pretty sure there is not much worry about the annular ring size in Kicad.
If you care to, check out application note AN4661 by ST Microelectronics (for F7 series, I’m using F746VGT6). On page 45 there is a point calling for keeping the same amount of vias in all SDMMC data bus lines which (in my humble opinion) suggests it might be a common practice for length matching in ~50MHz application layout.
This seems to be a good workaround for two layer boards if you are willing to sacrifice speed should the parasitics of the vias degrade the signals too much (my case).