My first try to design a SoC board-Please review, discuss about it! ( I have shared my design under CC BY-SA)

[sprhawk]

As you are mentioning Via in Pad, JLC has make this method free for users, are there any pitfalls when to choose to use it? for example vendor-lock (higher price by other manufacturer)? expensive in small amount production?

[sprhawk]

But I have to put SoC and one DDR on front, eMMC and another DDR on back

[m852]

The installation of parts on both sides of the production board is two separate devices in terms of cost, except for a few points… If we compare the cost of a multi-layer board with blind holes and mounts on both sides, then the first is cheaper in the end, all other things being equal.
For some RF devices, ordinary boards are not suitable FR-4 more expensive material with a specific wave resistance and other parameters is used there… In this case, the technology RF by reference is not suitable I think you understand why?

[sprhawk]

Thanks for tips! I’ll compare the cost of SMT

[m852]

You have enough space for full placement try to make a trace using general design rules, this does not mean that they are mandatory in this case you need to simulate… General Rules I wrote to you above

[sprhawk]

Fan out SoC by hand ( I know there is a plugin to do it automatically, but I want to do it as a practice )

[sprhawk]

I found KiCAD does not support drag diff pair, I cloned the source code to see whether I can put such a tool for that

[sprhawk]

I have sent my first Merge Request to KiCAD to fix one small issue

[sprhawk]

I found a standard mPCIe board is too small for my capabilities. I have to try to switch to larger size, 96boards as an example.
And I think I should change the board physical stack up to 1.6 mm

Changes to my new stackup

Setup more net classes ( after I changed my DDR schematic to hierarchical sheet, some of the net labels are seems to be incorrect named.)

Setup new custom Rules as the stackup

[sprhawk]

Route differential CLK_P / CLK_N

[straubm]

@sprhawk

for example vendor-lock (higher price by other manufacturer)?

Basically a 6-layer (that’s where JLCPCB offers plugged vias) PCB costs 3x @Pcbway and they do not even mention plugged vias (at a first glance). So: yes, you will be chained to JLCPCB unless you want to spend a fortune.

[sprhawk]

For people reviewing my design and teach me, I decide to share my work under CC BY-SA license

GitHub - sprhawk/leaf-rv1126

[sprhawk]

Routed two DDR chips. I can continue to do length matching next

[LM21]

What kind of rules or limits your chips have regarding high speed routing? What kind of part placement do the manufacturers recommend
When you know the answers to these questions, you board has more changes to work.

[sprhawk]

It’s only DDR3 or DDR4, like around 1Ghz signal

I were trying to use JLC’s rules as manufacturer’s limit

[LM21]

But what DDR manufacturer says? Check their application notes about routing. 1GHz or DDR routes can have clear and strict rules how they should be routed. JLC does help there.

JLC does help there.

Edit: JLC does not help there.

[LM21]

I have messed my message. Sorry about that. JLCPCB knows how to make pcbs, they don’t know if those boards work or not. A PCB maker may notice some stupid errors, but not always even those.
Your, as a designer, job is to check if there are critical tracks, and how they should be routed. And then make your board so.

CPU and DDR manufacturers have application notes and other info about how the chips should be routed. That may well be critical.

You can always Google “routing DDR memories”, or something

[sprhawk]

Yes, I have learned, but I need some kindly heart one to review my drawing. ( Or teach me )

[JohnRob]

I’m not a high speed signal designer, however I know layout is critical.

You should Google “how to layout DDR4 memory module”. I didn’t post a link because there seem to be a number of good hits.

To get a taste of the theory look at presentation by Rick Hartley