Layer confusion CrtYd and Fab

I’m making some new foot prints. To help me out I’ve been looking at other pre made foot prints. It seems that F.SilkS layer will appear on the final PCB and is carefully kept off any pads. The F.Fab layer won’t appear on the PCB, it is used more for documentation purposes and can be used across pads. Am I correct in my assumptions about F.Fab?

F.CrtYd is a bit more confusing. All the descriptions I’ve been able to find call out:

Used to show how much space a component physically takes on the PCB

This seems very ambiguous. Does this mean that it is only there for visual reference while routing or will it generate DRC errors if another component’s CrtYd violates it?

Finally is there a layer that will give KeepOut like capability, meaning that if a trace violates the boarders it will trigger a DRC error and when the board is flooded with a copper pour it will keep the pour from entering the area? (for example if using a bluetooth module to keep the antenna area clear of GND pour)

F.Fab - yes, for documentation.

CrtYd is currently for visual reference only, not DRC checked, possibly might be in future?

Keepout layer would be a great idea, not currently supported. Recently I have realised this is a “missing feature” with respect to CAD tools like Eagle. It is logged on the bug tracker, I don’t recall seeing it on any road maps.

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CrtYd (Court Yard) is the space that is needed arround a part for the “Pck and Place” machine.
So if you solder the pcb by hand, this CrtYd is not that imnportant.


Yes it is. I think you will even need more space than a pick and place machine.
(Your solder iron needs to go somewhere. You also need a tool to hold the part while soldering.)


KiCAD classifies each of its layers as either a “copper layer” or a “technical layer”. (In my opinion, the soldermask and solder paste layers are a third category. They receive special handling by KiCAD and the following remarks don’t apply to them.) In reality, ANY of the other “technical layers” can represent anything you want. They have names which imply a particular function in somebody’s workflow process and documentation scheme, but in fact any of the layers could be used for any function. They take on particular significance only when you print or plot them and tell somebody (such as a board fabricator) something like, “Here, this Gerber file was derived from one of my board layers and it shows where I want silkscreen legend applied to the front side of the board.”. A clever designer’s PCBNew file might actually have two (or more) layers with front side silkscreen data, each written in a different language, and the appropriate layer selected for rendering into a Gerber file depends on where he intends to sell the boards made in a particular production run.

I believe KiCAD’s current DRC only checks features on copper layers. You are correct that silkscreen which overlays bare copper is almost always a Bad Thing. I have encountered footprints in the KiCAD libraries which have silkscreen component outlines placed on top of bare pads . . . . and DRC did not catch the violation. It’s good practice for a designer to visually go over the design, centimeter by centimeter, and look for silkscreen violations before declaring a board “Finished!”. The same is true for the board-edge setback requirements (typically 10 to 25 mils (0.25mm to 0.6mm) that keep copper features away from the edge of the board.

“Courtyard” is primarily a visual indication for the board layout person. It is intended to represent the space actually occupied by a component, plus an allowance for assembly equipment (automated, or good-old human hands) that must place the components, and possibly other clearance requirements such as the space needed to move a connector when it is mated or unmated. Except for the component body itself these values are somewhat ambiguous and subject to local “house rules”. Many (perhaps most?) pre-made footprints have no courtyard information at all, and those that do may or may not comply with the requirements of a particular application.

The Board Edge layer is almost always used to define the outline of the board. Some fabricators will ask for this as a separate Gerber file; others will ask for it on a particular, specified, Gerber file; and a few want it to show on all layers. Your board fabricator may ask for internal cutouts or oversize holes to appear in the Edge Gerber (or may ask for these in a separate file). As far as I know there is no DRC test applied to the Edge layer. (But a copper fill that overlaps the edge will usually stop short of the edge, by an amount equal to the zone’s “Clearance” parameter.)

The other layers have names that imply a use, but you may use them in whatever way suits you. Other users have explained their layer usage in old threads. I use “DwgsUser” for dimensions and board fabrication notes. “ECO1.User” is my assembly drawing. Many folks use the " *.FAB " layers to show component body outlines, reference designators and values (in a small font, that doesn’t grab visual attention like a silkscreen text does). On a recent board that had to fit into an irregular shaped enclosure, I imported a *.DXF of the enclosure outline and mounting hole locations into the “Margin” layer. On one board last year, “ECO2.User” contained some detailed mechanical assembly sketches, and a test procedure for the assembled board.

KiCAD defines “KeepOut” regions on the copper areas to which they apply. For your Bluetooth example, that probably means drafting the KeepOut on one layer and then duplicating it onto other layers. The “Zones” menu makes this easy. I personally prefer to see the KeepOut areas parked right there in the copper pours they affect, rather than bringing them up on a separate layer. I believe KiCAD’s DRC DOES check for electrical KeepOut violations, but may not squawk a physical component body that lops over into an area where components are forbidden.