Last Mistakes You Made On a PCB You Had Fabbed?


My very first ever mistake was not knowing that capacitors have pin numbers assigned to polarity. This did not affect the function of the board, but the silkscreen showed the opposite polarity.

My last Pcb misteaks:

  1. In a self-created SOT-23 footprint, the footprint had one of the pads not centered exactly right; the pad was within tolerance and still worked. Note: This might be due to the old nightly version I have.

  2. The SOT-23 part was an N-Mosfet. I should have learned from my prior board, that pin numbers matter. I used the pin numbers for the same part in a TO-220 package… DOH! The symbol name, DGS or GDS is important as this should correlate with the pin numbers of the package. As in D-pin1, G-pin2, S-pin3 vs G-pin1, D-pin2, and S-pin3.

Note: Maybe the quirky pad placement allowed me to remove the part and solder it back in 270 degrees counterclockwise and still have a usable prototype board!

  1. My design uses interlocking terminal screws. The footprints are fine, but the silkscreen I used for alignment of the interlocking parts did not work out after fabrication. Fortunately, my mistake was to place the footprints to far apart; every terminal screw could be populated.

  2. The issue of Silkscreen over copper. I knew that silkscreen was not allowed on top of copper. I intentionally put some silkscreen over the bare board. I did not know that “no silkscreen over copper” actually meant, “silkscreen only allowed within such tolerance inside of solder mask”.

Care to help others out to share where you had a simple mistake creep in?

Automatic copper pour refresh and DRC check

Last Mistake was to get the orientation of this LED’s in the belt wrong. They illuminate now the products inside.


Omitting the mechanical problem of placing a switch where its body interferes with a battery holder . . .

I forgot to enable the reference designators when I plotted the silkscreen layer on Gerber. The really embarrassing thing is that I did this AFTER my final review of Gerbers. I found a few places where silkscreen corrections were in order; after fixing them, I re-plotted the silkscreen layer, zipped the whole package and sent it to the board house.

(Many surface-mount boards now intentionally omit silk-screened reference designators, so I can tell the boss that I was experiementing with state-of-the-art design practices. :wink: )



My mistake was not changing KiCad’s default solder mask clearance of 7.87 mil, even though I set my trace clearance to 6 mil.

Notice how the trace running above the pads has a tiny bit of exposed copper as it runs by each pad. This ended up creating a short circuit when I soldered the connector onto the pads.


My most recent mistakes where: (That i know of/ where i know what the issue is.)

  • Having made the schematic wrong (Used the wrong 5V output of my chip which made it impossible to wake the chip up from sleep mode. Solution do not put it to sleep and design a new board for the next iteration.)
  • But mostly it was about making footprints wrong. (The mistakes listed below where for some time in the official lib because i submitted these footprints to it.)
    • Did read the tolerance specification of the JST connectors wrong / Did forget that the manufacturer has a tolerance for drill size as well as the through hole part has a tolerance for pin size.
    • Had too little clearance between copper for another connector for the footprint to have the same voltage specification as the connector itself. (320V needs 3mm clearance. For anyone curios here the bug report that gave me this information.)
  • Placement issues on the pcb:
    • forgot that a connector has a plug that might be larger than the connector. (phoenix mstb series connector) Now my footprints for these connectors have a note on user drawings where the plug will be and i use a 3d model that includes the plug. (If anybody else wants to use them they can be generated with these scripts)
    • I sometimes forget that i need mounting holes. So some of my pcbs end up either being a lot bigger then expected, having only 3 mounting holes or needing a complete rework only to add mounting holes.



Yes, D2 is only connected at one end.

This seems to be a KiCAD bug. I deleted D2 from the schematic, loaded a new netlist, but didn’t delete it from the board layout. it should have remained on the board, but unconnected. Somehow, though, it was in the rat’s nest, connected at one end, so autorouting connected it to a trace. Passed DRC without errors, both before and after autorouting.

See Strange behavior with unused component

I sent this to fab at Seeed in Shentzen. The board works; it just has an unused footprint.


An other one, not really a fault but really anoing:
Setting clearance to 150µm while not using solder mask but filled ground planes and lots of smd. No fun.


Getting uBlox NEO7M modules instead of NEO6M… naturally the SPI pin out differs from what I had on the board. Could test them somewhat via I2C (as that was connected by chance as well), but the RPi can’t do clock stretching, so screw-up-squared (found out after I had 3 boards soldered).
To rectify I made adapter boards that shuffle the pins around, to solder between the NEO7 and the boards for the remainder of the ‘run’.

Also got a mechanical dimensions wrong, noted down 62 instead of 67 mm for a diameter, which meant I had to adjust something by 2.5 mm


Last mistake I made was using the “standard” BGA-8 package from the kicad library with a component from Texas Instrument.

It turned out that there was another BGA-8 package specifically for Texas Instrument (not the same width) in the kicad library but the pcb was already assembled and the manufacturer came back to me with the missmatch.


I keep forgetting to check lead diameters. Generic footprints often need adjustment or are just wrong.
My last bad mistake was a transformer which ended up with pins swapped - there is no standard for pin numbering on these


I somehow managed to use 2 different footprints (one was all uppercase, one all lowercase) for N MOSFETs. The bad footprint had the D and S switched. Took me hours to figure out why my simply mosfet circuit wasnt working the way I expected. Big fat facepalm moment. Really annoying mistake to require a respin, only problem I’ve found so far too.


I’ve done that.

You’d think the MOSFET industry would standardize this, but no…


It’s not just MOSFET’s. Of the 6 possible ways to assign BJT elements to the leads of a TO-92 package, I believe 5 of them have been used on some device. And once you get away from the venerable 78xx series, three-terminal regulators require a careful study of the data sheet before you assign a footprint.



Getting Narrow vs Wide SOIC is another popular error
Hard metric Nx2.5 mm pitch connectors vs Nx2.54mm Imperial based- not easy to see in smaller sizes


This was a bug in OpenGL canvas showing 0 unconnected but actually there was unconnected in Default View …

Fixed with soldering a small wires between the Gnd pins.


Did this error escape from DRC? (Be honest now . . . did you run DRC after the very last edit, before plotting fab files?)

But before anybody sees this patch (especially your supervisor) . . . get a slightly longer piece of that wire. Pull the insulation off, and twist the center into a small loop, about 1.5mm (60 mil) diameter. Solder in place, and label it “TP0” if you wish. Clip the ground lead from a 'scope probe to it. Even somebody who knows what he’s doing will never know about your oversight. (And in exchange for a serving of my preferred malt beverage, they will never find out from me!)



Whoaa! That probably would have fooled me for several days had that been a failure.

Very sneaky!


I had a client cancel a schematic review just prior to sending a board out to be fabricated and assembled, apparently because he wanted to impress a customer with the fancy furniture in his conference room rather than meet them in his office. The CPU on this board assumed it addressed 16-bit wide data, and when wiring an 8-bit wide Flash ROM you had to connect the CPU’s A-1 pin (yes, “negative one”) to the ROM’s A0 pin, the CPU’s A0 to the ROM’s A1, the CPU’s A1 to the ROM’s A2, etc. This was not correct on the schematic. I’d flagged the error, but I’m “only” a software engineering consultant and my input was not considered important enough to reschedule the review.

Of course the boards didn’t work, and the client couldn’t afford to respin the already-assembled prototype boards. We ended designing an adapter board for the Flash ROM that had holes positioned over the vias on main board and stitched the two boards together with fine wires. Because the vias on the main board were so tiny the only wire we could find that would fit through were individual strands extracted from some very flexible Cat-5 cables. A serious nightmare, but we did get most of the prototypes to work.


The worst I’ve done myself was to measure the distance between pin 1 and pin 60, and divide by 60 to get the spacing between individual pins. Yes, there are 60 pins, but there are only 59 spaces between the pins. Fortunately the leads on the component were long enough to handle the error.

Click here for my blog post about this goof.


I’m working to keep remembering that from 0 to 10 is actually eleven. It does matter in the code.