KiCAD Python API for YAL file generation

[choltz95]

Hi,

I am trying to leverage the KiCAD 5.0.2 python api in osx to produce simple YAL files (specification here: here) that describe a board layout. I want to do this so I can leverage a variety of autoplacer softwares which required YAL file input.

In particular, I have been able to produce a list of modules, their positions, and input/output pads for each module. However, I am struggling to produce the “Parent” module which represents the interconnections between modules on the board to be placed and routed.

I wanted to use the functionality described in the doxygen doc to retrieve all board connected items (pcbnew.BOARD.AllConnectedItems, however it looks like there is a memoryleak somewhere in the underlying KiCAD code.

swig/python detected a memory leak of type 'std::vector< BOARD_CONNECTED_ITEM *,std::allocator< BOARD_CONNECTED_ITEM * > > *', no destructor found.

I am quite new to PCB layout design. How can I retrieve the information to generate such a Parent module - i.e. how can I get produce the board iolist & network? I would appreciate any help at all! Thanks!

[qu1ck]

That memory leak warning is irrelevant.
The reason you can’t use that method to do anything useful is because it is not wrapped in swig properly. I was able to fix this with a small patch, just add
%template(BOARD_CONNECTED_ITEM_Vector) std::vector<BOARD_CONNECTED_ITEM*>;
in board.i.
But all that method does is concatenate list of tracks, modules and zones and return it to you. I am not even sure why tracks are included but vias are not, even though they are connected item too.
So it’s not very useful.

I have not read YAL spec but information you are looking for can be pulled from footprints board.GetModules() and their pads. They have GetNetname() and such.
Also board has GetNetInfo() which returns object describing nets on the board. That should get you started.

[choltz95]

Thanks a bunch for your response. I’ll get back to you after I explore your advice.