KiCad Push Pull Roujter, Pad Stacks

Hi,

I am usng KiCad BZR 6078. I am on linux Centos 7. My question concerns
Pad Stacks and the Push-Pull Auto router.

Background

I have a 2x23 IDC Dupont Pin header with 0.1 inch spacing, a Beagle Bone Black
header. This header has circular through hole pads of two rows and 23 columns.
I am trying to make a cape. I would like to be able to route to pins through
one row of the 2x23 pin header, instead of going the long way around the header.
I am using a two copper layer board.

What I decided to try and do was to have one of the rows with Pads on the
F.Cu (Front Copper) and B.Cu (Back Copper), and the other row with
just F.Cu (Front Copper). The idea being to get at one row I use F.Cu,
and to get at the other row I can use B.Cu and route underneath the
first row of F.Cu pads.

Issue / Problem

When I hit F11, and use the OpenGL push pull router, the router always
goes the long way round, even though there are no B.Cu pads to stop routing
directly. Here is a snipped from the BeagleBone Black kicad_module file.
If you observe pad C12, this has only Front Copper, but pad C13 has both
Front and Back Copper.
(module BeagleBoneBlack4Woofie (layer F.Cu) (tedit 55CBE1AF)
(tags “beaglebone black”)
(fp_text reference U? (at 0 1.778) (layer F.SilkS) hide
(effects (font (thickness 0.3048)))
)
(fp_text value “BEAGLEBONE BLACK” (at 0 -1.143) (layer F.SilkS) hide
(effects (font (thickness 0.3048)))
)
(fp_line (start 22.86 -6.35) (end 22.86 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start 22.86 -6.35) (end 43.18 -6.35) (layer F.SilkS) (width 0.15))
(fp_line (start 43.18 -6.35) (end 43.18 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start 43.18 11.43) (end 22.86 11.43) (layer F.SilkS) (width 0.15))
(pad M1 thru_hole circle (at -37.465 -20.955) (size 4.572 4.572) (drill 3.175) (layers *.Cu *.Mask F.SilkS))
(pad M2 thru_hole circle (at 28.575 -24.13) (size 4.572 4.572) (drill 3.175) (layers *.Cu *.Mask F.SilkS))
(pad M3 thru_hole circle (at 28.575 24.13) (size 4.572 4.572) (drill 3.175) (layers *.Cu *.Mask F.SilkS))
(pad M4 thru_hole circle (at -37.465 20.955) (size 4.572 4.572) (drill 3.175) (layers *.Cu *.Mask F.SilkS))
(pad C1 thru_hole rect (at 23.495 -25.4) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C2 thru_hole circle (at 23.495 -22.86) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C3 thru_hole circle (at 20.955 -25.4) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C4 thru_hole circle (at 20.955 -22.86) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C5 thru_hole circle (at 18.415 -25.4) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C6 thru_hole circle (at 18.415 -22.86) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C7 thru_hole circle (at 15.875 -25.4) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C8 thru_hole circle (at 15.875 -22.86) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C9 thru_hole circle (at 13.335 -25.4) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C10 thru_hole circle (at 13.335 -22.86) (size 1.8 1.8) (drill 1.1) (layers F.Cu F.SilkS F.Mask))
(pad C11 thru_hole circle (at 10.795 -25.4) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
(pad C12 thru_hole circle (at 10.795 -22.86) (size 1.8 1.8) (drill 1.1) (layers F.Cu F.SilkS F.Mask))
(pad C13 thru_hole circle (at 8.255 -25.4) (size 1.8 1.8) (drill 1.1) (layers *.Cu *.Mask F.SilkS))

Could there be a bug / feature in the push pull router that always sees all the Pads on a “thru_hole”
even though they are on one layer only? The router seems to refuse to route through on the Back Copper
even though there are no pads there in the way.

Is there something else I had to do to tell the auto router that it is OK because we are on the Back
Copper and it is OK to route underneath the Front Copper pads?

I looked at some posts regarding PadStacks, and noted that PadStacks are a sort of a newish concept
in KiCad.

Thank you for your kind help.

Warmest regards, Mike.

  • What’s the reason for creating through-hole pads with copper only on one side (in a double-sided, plated board)? During manufacturing, a hole without an antipad would be etched out…
  • The P&S assumes a through-hole pad has the same diameter on F/B layers. This can be changed, though…

Tom

Hi Tom.

The reason for copper on one side only is for routing purposes. If we have two rows of pads, and they are large, are we also wish to route larger traces in between, they interfere with each other. Image two rows of pads like this:

[An 74LVCH244 chip]

IIIIIIIIIIIIII <— the inner pads
oooooooo <— the outer pads

If I want to route to the 74LVCH244 it is easy to get to via the inner pads. But for the outer pads I either have to go around, or I have to go through the inner pads. So the idea was to route from the outer pads to the 74LVCH244 on the under-side where there is no Inner side pads placed, i.e. there is a “clear shot”.

Likewise if you had say a 4 layer board, we would want “easy” access to pads without interference by routing on one of the less congested inner layers.

I think I am OK for now in that I understand that the Push-Pull Router just assumes any pad occupies space on all layers, even though that pad is on a single layer only. I presume DRC would be OK. So the work around would be to route the first bit of trace using F9 normal view so that we are clear of the pads, and then go push pull auto router from there on.

Hope this makes some sense. I am a bit new to all this stuff and took me a while to understand the “Three Dimensional” aspects of a multi layer board.

Warmest regards, Mike.

Hi,

Oh I did not know that it might not be mechanically sound. Hmm that is an issue.

The Pads are not for IC but for an IDC Dupont 0.1 inch grid standard connector. So maybe the pins and pads are larger hence the problem. I will try a neck-down to 8 mills to see if it is happy at that level …

Best, Mike.

This is where I got the Foot-Print from. Maybe I need to tweak it a bit an make the pads smaller like you said.

Incidentally if I have a 4 layer board. How can I hook up using an Inner-1 Copper layer? Do I specify that I connect via an inner layer of copper? From the Pad package it looks like I can only specify (a) Front or (b) Back Copper. Maybe there is a way to specify different size pads for the same Pin, but on different layers using the S-expression file?

Hi,

I swapped out the pads for slightly smaller ones and that did the trick. I can now route a 10 mills track between the pads.

Thank you for your kind help.

Warmest regards, Mike,

Hi Andy,

Hope this picture works OK. Here are my design rules.

Best, Mike.