KiCad PCB power planes - how do they work?

I am trying to learn how to design PCBs in KiCad. I want to design a two layer PCB but can’t understand how to use power planes or fill zones.

  • I added a filled zone and selected bottom layer (B.Cu) and then filled it with GND net.
  • I then added another filled zone and select top layer (F.Cu) and filled it with +3.3V net.

Can I now drag the +3.3V and GND component connections and if I press V will they automatically connect to the relevant plane? Am I even doing this right because the signals are also on the top layer (F.Cu). Can you have one plane do two things (i.e. +3.3V and signals in my case)? Thank you.


yes, but as you add new connections, the plane will become more and more ‘interrupted’, and at a certain point the plane will not be able to connect different areas anymore (creating ‘islands’).

1 Like

Most my PCBs are 2 layers. In such case I have full GND plane at bottom (no other tracks there) and all signal tracks and power tracks at top. Free space at top I fill adding also GND zone for the whole top layer and connecting GND islands at top with continuous GND at bottom.
An example of such PCB:

All via you see are GND. There are few 0Rs to jump with VCC over other tracks.

1 Like

Typically on a 2 sided board (with no inner layers). The bottom is ground plane + horizontal traces, the top contains the +V and vertical traces. The horizontal traces will “cut” through the ground plane so they need to be minimized and make sure the horizontal traces don’t completely cut through the ground plane.

It is likely impossible to have all the signal traces on the top side of the board. So some will have to be on the bottom. Often vias (connections from the top to the bottom) are used to “stitch” a trace to the bottom to get past some on the top traces.

You can get an idea from this board.



1 Like

What is the benefit of filling free space at the top with GND too? I am using vias to jump over tracks but a 0R link would be a better idea.

As I am just learning, I am also using vias to connect to test points at different parts of the board. For example I have a via connected to a test point hole that I could solder too. I keep getting warnings saying via is not connected or is only connected on one layer. I dont understand this, I only want it connected to one layer (the +3.3V layer). I have filled this top layer with +3.3V net and then put a via to the test point, I am not sure why it won’t be connected?


Your test point is a THT pad, and itherefore it already connects to all layers (with a zone of the same net). You can also see the thermal spokes that connect your testpoint to the plane. The via also connects to this plane, but the other side of the via has no connection at all, and therefore KiCad issues this warning.

You can better visualize this if you look at it in the 3D viewer (with [Alt + 3]) and then fiddle a bit with it’s settings For example hide the board itself and the solder mask layers so you can look “inside” the PCB.

In past (90s…2006) I was using vias to jump with some tracks so had holes (sometimes longer if tracks at bottom were longer) in bottom GND. I was adding top GND to ‘compensate’ these holes.
When I decided to not break my GND I just left GND at top without great background on this decision.
But my thinking is: at 2 layer 1.5mm PCB you have bottom GND 1.5mm from your top track, but when you add top GND it is 0.25mm from your track whenever possible. It can be better return path (current surrounding smaller area) if it happens that this GND is along the whole track.
And not sure but I think I have heard that it is good if there are no big differences in amount of PCB surface covered by copper at both sides. It’s possible that it’s about the PCB bending during soldering in the oven, but I’m not sure.
If there are no reasons to minimize GND area I have one GND zone for the whole PCB specifying both sides.

1 Like

His via is connected to plane and has a track at other side connecting to test point. I don’t know why there are warnings. May be a bug in KiCad version (?) used.

Nope, both the track and the plane are red, a.k.a F.Cu.

So does this not mean that I don’t need a via for the 3.3V test point, it is already connected to the top layer filled with a 3.3v net?

Yes, you can see that in the image you posted - look at the red fills connecting to the pad.


You are right. Now I see it.

You don’t need this via. Your test point is connected to zone with 4 tracks and you add 5th track connecting to zone and some distance from that connection you have via going (from zone, not from track) to nowhere.
I was confused because you have a different zone color (opacity) and a different track color. I work with both of them set so as not to see the path supposedly running through the zone, when in fact it is the same copper.

1 Like

Makes sense. Thank you everyone for the help.

Right, this is the so-called Balance Copper Distribution. In addition to reducing ground line impedance and voltage drops a balanced distribution avoids Bow or Twist formation.