I tried to extend a trace and add a large sized via at the end, as a test point (for scope probes).
When I sent it to seeed, they promptly caught the issue that my via had “no solder mask opening”, which obviously would not be suited as my test point.
I read on this forum that there is “do not tent via” option when generating gerber file. But I only have one test point, the rest of the vias are just regular vias, and I like these be covered with solder mask.
The question is whether there is an easy way to insert test point/pad into a pcb layout.