KiCad, DRC Growing Pains

[BrendaEM]

As a newish Kicad user, my projects have been sent back dozens of hours by the changes in newer versions, much of it in the design rules checkers both for the PCB and also for the schematic.

While I do want Kicad to grow and evolve, I am greatly worried what will happen to archived projects–if I cannot even load last years design without problems requiring lengthy rework, library problems, and a confusing matrix of DRC choices.

I would give an “A” grade for the betterment of Kicad, but I would give a “D” grade for version migration. There were attempts, but the migration problems have been daunting even on two projects. While I don’t speaker for others, there are indeed others.

Lastly, if there was an option to save an (atomic file) with all necessary resources, I would use that.

[paulvdh]

There is not much comment we can give on those projects without more details.

KiCad V5 projects and earlier have some migration problems, because those projects depended on external libraries, and/or the default libraries of the installed KiCad version. After the transition of KiCad V5 to KiCad V6, there were quite a lot of people who had deleted (or not backed up) the [project]-cache.lib and [project]-rescue.lib libraries, while those have always been an inherent part of the project.

From KiCad V6 and onward these files are past tense. KiCad saves all used symbols in the schematic files, and all used footprints in the PCB file. KiCad does maintain links to external libraries, but updating symbols and footprints from those libraries is optional and must be explicitly initiated by a user.

The next most common cause is caused by improvements in KiCad. Newer KiCad versions have extended and more stringent ERC and DRC checks. As a result, they flag problems in projects that were already there, but older KiCad versions simply could not detect.

And there are a few things that are actually changing, and have the potential to break old projects. One of them is how far zones are retracted from the edge of the PCB. In old KiCad versions, the edge of the PCB was treated as track segments, KiCad retracted zones depending on line width and some clearance. The latest KiCad has a value for this in the board setup (For some time this default unfortunately was set to 0, which resulted in zones going right to the edge of the PCB and this is really bad, especially on multi-layer PCB’s). Net ties have also changed a bit.

@BrendaEM

Lastly, if there was an option to save an (atomic file) with all necessary resources, I would use that.

“all necessary resources” is wide and muddy. A KiCad V6 (and newer) has all symbols and footprints inside the project. This makes all the important stuff pretty much future proof. But there are still things that are not archived automatically within the project, such as:

• The paper layout file.
• 3D models.
• Datasheets, (they are just links in schematic symbols to somewhere else).

Because newer KiCad versions store symbols and footprints inside the project, it’s much more robust and future proof. KiCad also has options to export these resources into a external (project specific or global) libraries.

@BrendaEM

There were attempts, but the migration problems have been daunting even on two projects.

And again, without knowing more about the problems you encountered, there is nothing we can do. It is possible that you are attempting to fix things in the wrong way (KiCad has lots of ways to do things). It is also possible it could have been solved with a handful of mouse clicks. I used to have problems with upgrading projects, but as KiCad improved over the versions, and my knowledge of KiCad also grew, I don’t have such problems anymore.

So for the next time, I suggest you report back with the errors you encounter.

[Piotr]

I’m using KiCad since V 4.0.7.
I have started my play with KiCad from making my own libraries. With 4.0.7 I have designed only one PCB and it was practically only test. When I had my libraries ready V5 came so my first experiences are from V5.
I have never run ERC - so one of mentioned by you problems solved.
I don’t know what you mean under ‘library problems’.
If for old PCB one of new tests in DRC generates errors or warnings I switch it into ‘Ignore’.
For example I place my footprints touching one another so their silkscreen rectangles lines lie on top of each other. Because of this I have ‘Silkscreen overlap’ set to Ignore not only for old PCBs but for all PCBs.
Before doing next version of previous PCB I run DRC and decide which tests to set to ‘Ignore’ and for which I have to do some modifications. Than having this previous version giving no DRC errors I start to modify it into next version.
I have never thought of it as of a real problem.