Hello,
Getting errors on vias while running PCB DRC: Annular width (board setup constrains min annular width 4.00 mils; actual 0.00 mils), checking properties on this via: diameter=20 mils, hole=10 mils, AND Padstack mode=Custom. When changing Padstack mode to “normal” and running DRC again, the error disappears.
I have many vias in my design and don’t want to go over each and every one of them to change its properties… Why is this happening, and what is the difference - padstack mode custom vs. normal?
Thanks in advance.
Which V9 ?
Can you paste your version info here please, you can get it from KiCad > Help > About KiCad > Copy Version Info
Unless you are connected to, and are representing that pcb design company, we cannot let you use this username. Please PM me with an alternate choice, otherwise we will have to delete the account.
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Even if he’s affiliated with that pcb design suite, a username which reflects his role in that company would be a lot better. Just the company name is too vague imho.
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No problem, please change to “YoursT”
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Thank you for understanding. We a ‘grief adverse’. 
I edited two posts to remove the company name. Not because it’s a competitor, but to prevent this thread from showing up in searches on this forum, and this tread is unrelated to that.
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