Good question. Maybe it means the clearance between the maskless area edge and the nearest copper edge under the mask, to prevent exposing unwanted copper because of mask registration tolerance. I hope someone who really knows tells more about this because I haven’t even noticed this.
Many thanks for your guess concering the “Solder mask to copper clearance”. I was thinking about the copper of the affected pad itself. But I tried to increase the value and the reported errors are “solder mask aperture bridges items with different nets”, so your guess must be correct.
This is it. It is a constraint, not a control: Changing it changes the DRC results, but changing the expansion changes what is actually created on the mask layer.