(Please have a look to the two GND vias in the center of the clipping above)
I’m currently not sure why these Vias were not connected by a track in this case, but lets assume that it is important to pull GND separately from the inner layer.
My problem is that the DRC did not found this - and I did not found a way how to configure the DRC appropriately. Is there a way? Thank you in advance
At first moment I thought that I have many times put vias so close and no complains. But at second moment I understood that I always put GND zone at top and at bottom so even I see vias being so close they are really connected by zone. I don’t know if DRC can find it, but I think that if you add GND zone you will avoid such problems.
der.ule Under File->Board Setup, you will find the minimum distance between two holes,
with the standard parameter of 0,25mm this vias do not disturb the DRC
Thank you for this tip! If all vias share the same width of the annual ring, this will be a good solution. Otherwise we need to use the annual ring with the max. width to calculate the min. distance between two holes. For all other vias, the DRC might report a problem if the min. copper to copper distance is not violated.
Piotr
At first moment I thought that I have many times put vias so close and no complains. But at second moment I understood that I always put GND zone at top and at bottom so even I see vias being so close they are really connected by zone. I don’t know if DRC can find it, but I think that if you add GND zone you will avoid such problems.
Thank you for this idea! It might be a good workaround for many cases.
We are designing a 4 layer PCB, where one of the inner layers is used for GND only. GND should be routed starlike, using the inner layer as single reference point. This means that we should avoid to route GND on the top or bottom layer whenever its possible. Instead, we should pull GND from the inner layer to the top layer using a via.
Having a GND zone, we will get additional GND planes on the top layer, even when we do not want them.
In my opinion in most cases solid full GND layer is better then starlike (but only in most cases).
Even if you really need starlike I don’t agree with “This means…”.
I will tell how I would do it using my old Protel (the same can be done in KiCad, KiCad solution is more flexible, but because of this flexibility needs a little more work to do that, I think (I didn’t do that in KiCad yet).
In Protel 3 I have “Keep out” layer (but don’t have keep out zones at copper layers). Anything I draw at that layer will block copper at all layers. So drawing some lines at that layer I will decide how is the starlike organised. Then I can put GND zones at all layers and all of them will follow that starlike structure. I would add via stitching to make GNDs at all layers working together.
Additionally as no copper is allowed to cross with anything at Keep out you will have guarantee that all signal tracks are layed just over theirs return path.
I have never designed more that 2 layers PCB, at my PCBs at bottom I have no other signals than GND, but I always fill GND at top also.
But with 4 layers (I plan) when I will have GND and VCC at inner layers the GND vias being too close at VCC layer can really be a problem I have never thought about before. I think adding less priority GND zone at VCC layer can be used to just connect GND vias if it happens them to be to close. But how to ensure myself to do it before getting complains from PCB manufacturer
Piotr In my opinion in most cases solid full GND layer is better then starlike (but only in most cases).
Even if you really need starlike I don’t agree with “This means…”.
Sorry, this was a misunderstanding. It is a 4 laer PCB, where the inner layers are GND and VCC. I described this as “starlike”, using the inner layer for GND as single reference point. But I see that this was a bit confusing.
I think a python script should be able to find vias placed too close together. We will try to implement one.
