Please update your macos torrents. They have been updated.
f392321af0513a5c6920bb89ca7831c7 kicad-unified-5.1.0-10_14.dmg
923c7107d8479d340a0a663f87a32441 kicad-unified-5.1.0.dmgYep, already downloading new file.
EDIT: updated.
I started torrenting last night (after your updated message) and am now seeding. I just verified the macos torrents that I got match nickoeās updates.
Not many seeders yet. @nickoe is it possible to add the torrents to the download web page?
The Ubuntu 5.1 PPA contains just the application and demos.
For some reason the symbol, footprint and 3D libraries used are from last year
edit
The 18.04 PPA does contain up to date libraries. My problem was the package manager needing some older versions to be manually removed first, an apt problem, not the PPA
Wow! The accelerated rendering in eeschema is a huuuge improvement for me on OSX. Schematic capture was my biggest churn because of the old sluggishness. This is great! Applause!
Just got 5.1 installed on two computers. All I can say is AAAAAA SHINEY ACCELERATIONā¦ but waitā¦ AUUUUGHHH WHY
Oh to hell with it, ignore my entire belowā¦ I guess my whole sense of how netlist import/export was done before is now deprecatedā¦ PcbNew: changes from 5.0.2 to 5.1.0 == Ignore everything below here
1) Creating a netlist now pops up an extra dialog box asking where to save the file. This is a mild annoyance, but thereās no way to say āJust save the netlist to blah.net and donāt bother meā. Or is there a new feature Iāve missed somewhere that can negate this? (Verified new behavior in both 5.1 / Ubuntu 18.04LTS and Win10). More mouse clicks = bad juju in my dogma.
_2) Could someone explain the new way netlist gets imported for reference designators? Previously, one could import netlist with timestamp and reference designator. This not-often used but very powerful feature would allow one to completely re-annotate a schematic and update a PCB without munging the layout. This is very useful when doing a highly dynamic design that changes a lot, and you want to make the reference designators a little more sane/clean. What I would typically do is save schematic, export netlist, import to PCB, make sure everything is clean, DRC passes, etc, and Save a backup. Then go back to schematic, and wipe out the entire annotation of the PCB and re-annotate so everything makes reasonable order-sense. Then back to PCB, but instead of importing by refdes, Iād import by timestamp. Ta-da, all the refdesā get changed, but the layout remains the exactly the same. _
So, is āKeep existing symbol to footprint associationsā == Timestamp, and the second (no longer default) option by reference designator?
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