JLCPCB Design Rules

Hello.
I apologize for starting a topic about this but I’m inexperienced on PCB design.
So I’m checking my net classes to fill JLCPCB design rules but I have some doubts.

Min Trace and Spacing is direct.
Min. Via Hole Size is Via Size in kicad ??
Drill Hole Size is Via Drill in kicad ??

The rest I don’t know. Can you help me?

Once again, sorry for starting this newbie topic.

Best resgards.

Just set the values larger than the JLC minimum. You don’t want to have traces at the minimum unless you really need to.
I’d suggest you design in mm rather than inches. That way you won’t make conversion mistakes.

Min hole size is for component pad holes.
A Via is where a trace goes from front to back and there is No component. Remember that nomenclature.

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I have a design template for JLCPCB at https://github.com/sethhillbrand/kicad_templates that uses their rules for KiCad DRC. You might find that a useful starting point

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First of all Thank you Both @iabarry and @Seth_h for the replies.
About the templates i was looking for one yesterday and here it is thanks to you @Seth_h.

Also what I wanted was a bit of a 1-to-1 conversion because I know what is a Via and Trace. I just don’t know where to change that value. If I know that I will know what I’m doing eheh.

Let me give an example:

JLCPCB Rules --------------------------------------- Kicad Net Class

Min Trace --------------------------------------------- Track Width
Min Spacing-------------------------------------------- Clearance
Min Via Hole Size------------------------------------- Via Drill
Min Via Diameter-------------------------------------- Via Size
Via to Trace---------------------------------------------- Where to change that?
Drill Hole Size-------------------------------------------- Where to change that?
Hole Size Tolerance------------------------------------ Where to change that?
Anular Ring -----------------------------------------------Where to change that?

Also I know what µ stands for but what is the difference between “Via Size” and “µVia Size” and when to apply that.

Same for differential.

Best Regards

Vias come in original and extra crispy. Oh wait that’s KFC.

The are normal and tiny vias. Since you seem new to this, just use a regular via with a pad diameter of 1.5mm with a 0.5mm drill. This makes the via a good test point when debugging.

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This seems like a good thread to continue a discussion on JLCPCB rules. In Kicad board setup, Net Classes, I can set a ‘Clearance’ but it’s not clear what the clearance value refers to in respect to the overall set of minimum clearances JLC give. I have used the template kindly provided by Seth_h which has a clearance of 0.127mm and this correlates to JLC’s minimum spacing for tracks - there must be at least 0.127mm between the nearest edges of tracks. It also has a minimum hole to hole of 0.25mm although JLCPCBs minimum is 0.5mm (that’s easily fixed.)

However, JLCPCB also has minimum clearances for via to via, pad to pad, via to track, pad to track etc. In all cases, these minimums are greater than 0.127mm - for example, minimum clearance via to track is 0.254mm. I accept that Kicad is not specific to any one manufacturer so I’m not expecting the design rules to match to JLCPCB rules.

I can’t find anywhere that this has been answered so: given there is one place that I can see where clearance can be set up and the need to provide different clearances for different elements on the board, what is the advice? The largest clearance on JLCPCBs capabilities is 0.54mm for pad to track but that seems to be a rather large value to use for all clearances. Would we take each clearance value one at a time and add to Board Setup, run DRC and check if any errors are specific to that value, e.g. set it to 0.54mm, run DRC and check if any errors are flagging up for pads and tracks specifically, ignoring others; repeat for via to via; repeat for via to track etc?

Edit: I understand that clearance in Kicad is between nets; JLCPCB only make the distinction on net clearance on their hole to hole and via to via capabilities.

I’m not familiar with JLCPCB’s design minimums, but any minimum to a via or to a pad is the measurement at the via or pad from the edge of the annular ring, edge of the hole, or center of the hole? Also, by “pad” do they mean THT pad or SMT pad, or both? (In my first question I was possibly erroneously only considering THT pads.)

By pad they mean either and they measure from edges to edges except for hole-to-hole which is measured from the edge of the hole.

What I’m trying to work out is how best to use Kicad to check all required clearances. I can put 0.127mm into the ‘clearance’ field in the Board Setup for the Net Class, run the DRC and this will tell me if there are any bits of copper closer than that: 0.127mm is the minimum track-to-track clearance so that confirms that. They have a minimum 0.254mm via to track clearance and they only way I can think of confirming that is to change the net class clearance to 0.254mm, run the DRC and ignore all the errors except those that state that a track/via is too close to each other. Then there’s pad to track which requires a 0.54mm clearance so repeat for that. And so on.

Here’s what I do and jlcpcb manufactured my boards without issue:
Set net clearance to 0.2mm and ignore the via or pad to track.

This rule is simply bullshit, they have no reliable way to know what is a pad and what is a via and there is no reason to treat them differently.

0.2 mm is good enough for hobbyist designs. If you need more density I would design your board with largest clearance you can and then find a fab that will manufacture it for you. Once you get to that point you can pick a more professional fab that doesn’t publish figments of someone’s imagination as rules.

I have seen that all communcation from the big cheap Chinese manufacturers is unreliable – not because they don’t know, but because they can’t communicate in English very well. Or maybe in Chinese either. Therefore we have to give them benefit of doubt - maybe the rule means something else than what it seems to mean.

(Read through the FAQ/Support articles of the two big to see what I mean. You probably won’t know anything more about the subject matter after reading an article but may be even more confused.)

I suspect that sometimes “via” and “THT pad” are differentiated by the hole size. Whether it’s a reason for something, I can’t know.

But back to the question…is the only way of testing the clearances, according to their published capabilities, to change that clearance value against the netclass, run DRC and look for errors specific to the clearance value and ignoring others; rinse and repeat?

qu1ck wrote on via pads

This rule is simply bullshit, they have no reliable way to know what is a pad and what is a via and there is no reason to treat them differently.

I beg to differ.

  1. The fabricator can know where the via’s are. KiCad tells them in the attributes in the Gerber file.
  2. The fabricator needs to know where the via’s are. Via drill holes have other tolerances than component drill holes, per IPC spec. The solder mask is handled differently around via’s than component holes, per a whole bunch of IPC spec – logical, mask on via pads is desirable, but one would not want mask on via pads.

Of course, the etching and plating process does not ‘know’ what are via’s and what are other pads. Neither does it ‘know’ if something is a trace, a pour or a pad. The difference in clearances between pads and traces is not there for the etching/plating, but for the mask. As the relation between via pads and other pads and the mask is different, it is logical the clearances is different.

I had a quick look at the JLCPCB design rules. I find them well done, and very logical. (No, I do not work for JLCPCB.)

I don’t see logic in here. Anything related to mask is described in mask minimums. Gerbers also have information on which holes are covered and which are not, there is no need for fabricator to do more.

This doesn’t mean fabricator needs to know where the vias are. They can just have tighter tolerance of the two for both and that’s it. In fact jlcpcb publish hole tolerances as single common value for all holes.

Again, controlled by gerbers, not the fab (unless you explicitly ask them to change something which is a great way to f*** up your order).

The different copper clearances on pads are there to meet the solder mask design rules. Theoretically you are of course right that if the solder mask is perfect, the fabricator should not care about these specific clearances.

Idealistically and theoretically, fabricating to the image seems ideal. The reality is far different.

This is right if the fabrication data is guaranteed perfect. Then the fabricator can fabricate according to the image. In reality, a large number of data sets, maybe more than 50%, contain errors, often gross errors such as legend on pads, footprint errors, vias closed on both side in the mask, NPTH hitting copper, poor alignment between drills and copper, and so on. This is the real world. Fortunately fabricators check before they fabricate, and correct the error, with or without telling the customer. Depends. The fabricator does a lot for you. Help him by providing complete, even redundant,

Fabricating according to the image works best in simple boards and low volumes. If you set all clearances to a max, as was suggested here, all will be fine. And indeed, if your design allows is, please do. But for tighter boards this no longer works. You need to push the envelope, and the fabricator needs to tweak the boards to maintain yields. For example, the mask is then tweaked where the track connects the pad, or a pour connects to a pad, in order to optimize solderability. Of the question of solder mask clearance or width. These two specs work against another. The optimum depends on the fabrication process. It will produce better quality if you let the fabricator tweak the clearance to optimize the result. Overspecification increases cost and decreases quality. Of course, this is not done for a single 5$ prototype, but for volume it is. Have a little respect for a fabricator. He knows something about fabricating boards. He does it for a living. Help him to do a better job.

About the tolerance on via holes. You are right that JLCPCB does not state a different tolerance on via’s. But this is JLCPCB, plenty of other fabricators do. And the question is what JLCPCB means with their tolerance statement. I suspect this tolerance applies to component holes, and not to via’s. Communication problems were mentioned here. The JLCPCB engineer may reason: Everybody knows there is an IPC spec on via holes, why bother writing this on the website – it is just cluster that will confuse our customers.

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I can see your points but I still maintain that if a restriction is due to soldermask limitations it should be expressed in soldermask tolerances and minimums, not in an obscure copper clearance setting that a) most programs probably don’t support and b) they don’t respect themselves as they clearly fabricate a lot of boards with less than 0.54mm pad to track clearance.

I guess they do not rely on the supplied mask for a significant portion of the jobs, and tweak it to suit their needs, hence their interest in the underlying copper rules. However, I agree with you, specifying something their customers cannot meet, or verify, makes no sense.
They found other ways to confuse their customers than via hole tolerances! (-:

Notwithstanding viewpoints, opinions and past experience my take is this. If JLCPCB specify a minimum clearance tolerance they do it for a reason and I’m happy to set out my boards accordingly - why do I want to go to the hassle of doing otherwise just to have it picked up when submitted and then have to rework layout etc.

But I’m still no clearer on approach because my question is being subverted by discussions on the rights-and-wrongs of their capabilities that they determine and they advise to customers. This is a question on Kicad capability not on manufacturing capability. On the basis of multiple different clearances required I can’t find any other way of doing this except either (a) setting the Net class clearance to the ‘max’ minimum clearance and having everything subject to it; or (b) setting it individually, running DRC and only looking for errors specific to that value - rinse and repeat. Neither way is ideal really but if it’s all that’s possible then I’d go with the latter and run DRC a lot more often during layout.

Has anyone got an answer?

Probably not for v5.1. Version 6 will be very different in this respect, see Need some guinea pigs for a rule-based DRC <<PROTOTYPE>>. If you don’t find an answer there you can ask.

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