The different copper clearances on pads are there to meet the solder mask design rules. Theoretically you are of course right that if the solder mask is perfect, the fabricator should not care about these specific clearances.
Idealistically and theoretically, fabricating to the image seems ideal. The reality is far different.
This is right if the fabrication data is guaranteed perfect. Then the fabricator can fabricate according to the image. In reality, a large number of data sets, maybe more than 50%, contain errors, often gross errors such as legend on pads, footprint errors, vias closed on both side in the mask, NPTH hitting copper, poor alignment between drills and copper, and so on. This is the real world. Fortunately fabricators check before they fabricate, and correct the error, with or without telling the customer. Depends. The fabricator does a lot for you. Help him by providing complete, even redundant,
Fabricating according to the image works best in simple boards and low volumes. If you set all clearances to a max, as was suggested here, all will be fine. And indeed, if your design allows is, please do. But for tighter boards this no longer works. You need to push the envelope, and the fabricator needs to tweak the boards to maintain yields. For example, the mask is then tweaked where the track connects the pad, or a pour connects to a pad, in order to optimize solderability. Of the question of solder mask clearance or width. These two specs work against another. The optimum depends on the fabrication process. It will produce better quality if you let the fabricator tweak the clearance to optimize the result. Overspecification increases cost and decreases quality. Of course, this is not done for a single 5$ prototype, but for volume it is. Have a little respect for a fabricator. He knows something about fabricating boards. He does it for a living. Help him to do a better job.
About the tolerance on via holes. You are right that JLCPCB does not state a different tolerance on via’s. But this is JLCPCB, plenty of other fabricators do. And the question is what JLCPCB means with their tolerance statement. I suspect this tolerance applies to component holes, and not to via’s. Communication problems were mentioned here. The JLCPCB engineer may reason: Everybody knows there is an IPC spec on via holes, why bother writing this on the website – it is just cluster that will confuse our customers.