I’m new to PCB design, which is probably a good thing to keep in mind when reading my problem below.
I want to create a board which contains an ST LSM6DS IMU with a LGA-14L footprint, and I was intending to have JLCPCB produce it. But, it seems that the footprint is not compatible with the 0,127 mm clearance that I think JLCPCB requires. If I put in 0,127 mm in KiCad, the ERC complains about the pad-to-pad distance of this footprint.
But I’m sort of confused since JLCPCB also have this component in their parts library, so it feels like I’m missing something. I looked at both the footprint from Digikeys library, and the one in standard KiCad libraries, and both fail the 0,127 mm clearance rule. Could the solution be to create a custom footprint with smaller pads?
No I think the ERC check works ok, it’s only 0,1 mm between the pads. I’m just confused since JLCPCB seems to have this part in their SMD parts library, which seems strange if they can’t actually produce PCBs to mount it on?
It might be a good idea to at lest link to the datasheet of the device in question and possibly give the full name of the footprint in the standard library and possibly also a link to the footprint provided by jlcpcb.
The part at JLCPCB is this: https://jlcpcb.com/parts/componentSearch?searchTxt=lsm6ds3. First I didn’t realize that I could see a footprint there, but they do have a EasyEDA library for the part and there I see how their footprint looks and it is indeed using quite small pads so I guess this is what I should replicate in KiCad.
So now I’m making my own footprint now based on the info in the datasheet. Should I create the pads with the same size as the actual component, or is there a benefit of e.g. making them slightly longer towards the edges of the component? Or maybe even a bit wider, but still narrow enough to meet JLCPCBs clearence rule? I couldn’t get any actual measurements from the online EasyEDA footprint viewer on JLCPCB, so I can’t see how they’ve done it.
If it makes any difference, I intend to buy a matching stencil and try to solder using a reflow oven.
Hm the appnote is written rather strangely. They suggest to make the land pad 0.1mm wider than the “lead”. However well the “lead” is given with quite a large tolerance for its width (0.15 to 0.35mm) and nowhere to they state which measurement should be used as the reference. I suspect they might mean to take the nominal measurement which would mean that the pad would then be as large as the “lead” at its maximum size.
I seem to remember that IPC would suggest 0mm of solder fillets all around. Which normally also results in a pad that is about as large as the maximum “lead” size. I assume the footprint in the official lib might therefore be made with the wrong IPC generator settings (it might reference the wrong fillet size definition). And i seem to remember that we had at least a pull request by @Evan_Shultz that would have fixed it but do not remember if it was merged (that pull request would have fixed all LGA footprints after we discovered this slightly hidden suggestion by IPC).
Note: I use the word lead here even for a lead-less package for lack of a better term that clearly differentiates the pad on the PCB from the pad on the chip package.
