I am getting some DRC errors that I think I can ignore based on some searches I have done, but I just want to check with the collective expertise of the group.
I have a 4 layer pcb layout with an MPM3610. I followed the recommendations in the datasheet on page 19 as best as I could.
The datasheet layout shows a pad attached to pins 7,8,9 for the output, and pins 4,5,6 (SW) probably for thermal reasons. But I get a 13 DRC errors for these connections. I have attached the report.
6 of the errors are "[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
6 are for â[clearance]: Clearance violation (netclass âDefaultâ clearance 0.2000 mm; actual 0.0000 mm)â
1 is for [isolated_copper]: Isolated copper fill - for the copper around the SW pins.
Do I have a defective footprint, and I should look for another one? Have I made a layout mistake? I also set the pins 7,8,9 and 4,5,6 as solid fill. Is that a mistake? DRC.rpt (3.6 KB)
clearance violation are most probably bad and should be resolved
isolated copper fill islands can happen - look into your design and decide for yourself, if the copper shape can be accepted or not
solder mask bridges items with different nets:
can happen as a result of clearnce errors on pads - so resolve all clearance errors first. sometimes the soldermask error then goes away
can happen as a result of fine pich packages. This canât be avoided if the pitch is smaller than the solder mask width.
regarding your specific issue: look at the drc report exactly, it tells you in detail which items are causing a clearance error. The error happens between pad 4+5+6 and pad 19 and between pad 7+8+9 and pad 20.
Without a attached project I canât provide better answers.
Just as a guess: maybe the symbol has no pins for pad19/20, therefore these pads (19+20) get the âno netâ attribute assigned and these âno netâ pads then shorting the other pads 4+5+6 and 7+8+9). Looks like you have downloaded symbol+footprint. Take this as initiation to draw your own symbol+footprint combination. With downloaded content you will see such mistakes again and again.
In KiCad you can use overlapping pads in a footprint as long as they all have the same pad number. So if you change the pads 4, 5, 6 and 19 to all have pad number 4, then you do not get DRC violations for that. You also have to change the schematic symbol, so it also uses the same pad numbers as in the footprint.
I think I have a bad footprint and symbol. Looking at the datasheet again and @paulvdh diagram from the datasheet, pads 19 and 20 are nowhere near pads 7,8,9 and 4,5,6.
I am confused by the blue areas around SW and NC in this layout suggestion from the datasheet. Are they copper pours?
I believe so. Since the inductor is integrated, it looks like a connection isnât necessary, but the datasheet says:
If you look at their eval board layout, they do fanout the SW pins to a remote pad, and the datasheet mentions hanging an R/C snubber on it to improve EMI.
Itâs OK to use footprints from âalternative sourcesâ, but you have to check them and possibly modify them. In your case, just renumbering the pads may be enough, but I would also verify pad locations and dimensions with the datasheet.
I am still getting the errors:
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets for pads 9,8,7 and 4,5,6
[clearance]: Clearance violation (netclass âDefaultâ clearance 0.2000 mm; actual 0.0000 mm) for pads 4,5,6 and 7,8,9
I also have 2 unconnected pads, but when I try to connect them to the layer 1 copper pour I created, Kicad wonât let me start the trace or connect it from the pour to the pin.
Pad 15 is also a mystery, as the only way I can eliminate that error is to remove the trace on pin 16.
I checked the AdaFruit MPM3610 board layout, and they put a copper pour around pins 4,5,6 just as I did. Since their board works, I assume that is a correct thing to do.
In the clearance constraint you have told kicad that there should be at least 0.2mm between 2 pads. And here they are touching, so they are 0mm apart.
The soldermask warning is here related to the same issue. But this is only a warning and not an error.
Once you have change the pad number on the footprint, you also need to update the symbol to reflect your modification (so in this case to remove the redondant pad).
OK, to make sure I understand you correctly. I have to change pins 4,5,6 to one number, and pins 7,8,9 to another number on both the symbol and the footprint?
Yes, I already mentioned that at least two times in this thread.
Exchanging one faulty footprint for another with similar faults will not solve your problem.
No. Not really. It is sufficient if all the pads are a part of the same net. I just verified this (In KiCad V8.0.9). See screenshot below. This does not give any DRC violations.
Maybe, but be careful with that. First, if you do this in the PCB editor, itâs easy to make mistakes. And copper zones are usually covered with solder mask, and you will have to remove this too.
Itâs better to either use a pad with a compatible pad number, or use the Pad edit mode (Look that up in the PCB Editor Manual.
I changed pins 4,5,6 on the symbol and footprint to 4. I changed pins 7,8,9 to 7 on the footprint and symbol to 7. I also tied pins 4,5,6 together and pins 7,8,9 together on the schematic. I still get the same errors. I am not sure how to proceed.
You have to modify the big object. As you can see from the screenshot in my previous posts, the small pads 1, 2, 3, 4 are all just fine. The trick is to give the big pad a number that is also part of that same net.
Or use the Pad Edit Mode (Read the manual first).
It also helps if you read the posts and study them a bit more until you fully understand what is written.
@paulvdh Thank you for your comments. After working through Pad Edit Mode, I was able to make the footprint work for pins 4,5,6 and 7,8,9.
I still have one last error regarding pin 15. I am sure it is another footprint bug.
[clearance]: Clearance violation (netclass âDefaultâ clearance 0.2000 mm; actual 0.1952 mm)
Rule: netclass âDefaultâ; error
@(115.7319 mm, 129.0540 mm): Pad 15 [unconnected-(IC2-NC-Pad15)] of IC2 on F.Cu
@(116.2319 mm, 129.0540 mm): Pad 16 [12V After IN260] of IC2 on F.Cu
No matter how small I make the trace into pin 16 I still get the error. Do you have any suggestions on how to fix this one?
Itâs the pad that is a bit too wide. If you make both pads 16 and 16 a few micrometer narrower itâs OK.
Edit / Addition:
Bertrand (Below) suggest reducing the clearance. On itself that is a valid solution, but 0.2mm is already a quite small clearance. Also, the âRecommended land patternâ in the datasheet is for pads with 250 um width, and the pitch is 500 um, which leaves a 250 um clearance.
you can reduce the 0.2 to 0.19mm. You clearance issue is with the pads and not the track. So even by reducing the track width, the pad remain the same.
2)you could also reduce a little bit the width of the pad 15 and the pad 16, by 0.01mm (that could be the best solution actually).
Thanks so much! That did the trick! No DRC errors!
Another question. I will have JLCPCB make the board. I went through their design rules on their web site and made as many changes to the Board setup as I could match their rules to the Kicad Board Setup rules. Is there another way to do it? I have seen two github projects that proclaim to have all the JLCPCB rules tied up in neat package, but I am not sure if that is the right way to go given my issues with third party footprints.
