Hello All,
I am trying to use this BGA package:
https://www.onsemi.com/pdf/datasheet/fpf3040-d.pdf
I made the footprint with the recommendations from the datasheet and JLCPCB capabilities:
Min. BGA Pad Dimensions = 0.25 mm
My problem is that I cannot route ball C2 with even the smallest trace (0.09 mm, 3.5 mil)
Does that mean I can’t use the part with JLCPCB?
Thanks
Can you attach the footprint here?
If the pitch between the pads is 0.4mm, and the diameter of the pads is 0.25mm, then there is a gap of 0.15mm between the pads. And then you want to divide that 0.15mm between the width of a track and a clearance of both sides between the track and the pads?
That’s not going to work.
The quick answer would seem to be no. If you have 0.4mm spacing between 0.25mm pads, you only have 0.15mm space between edges of pads. That doesn’t allow for 0.09mm trace + 0.09mm clearance on either side of the trace.
Edit: Oops, I was too slow, other people gave good answers first!
I think the package is not meant to be routed between the pads at all, but be used with vias on pads which is an expensive technology. JLCPCB won’t probably do that.
And in addition, you have other tolerances too.
If I look at the datasheet, it suggests 0.2mm pads, but 0.3mm solder mask opening:
Those are quite tight tolerances.
It also means the solder mask is only 0.1mm wide at it narrowest place.
If you want to put tracks in between you also want them to be covered by solder mask, and they also need a tolerance for misalignment between copper and soldermask.
So I don’t see how this is going to fit.
If you want to use this package you may need to use something like “Via in Pad” (which is not the same as just placing a via in a pad). With via in pad, the via’s are filled to prevent them from soaking up the solder. They can even be covered with conductive material to solder to, but I think that technique has yet another name.
Thanks everyone.
I sort of suspected that the answer would be no. Good to have these confirmations.
This parts shortage is wrecking havoc on my plans 
I was also looking at this, but Paul was quicker.
The solder mask opening being larger than the copper pad comes from the necessity of taking mask layer registration error into consideration, i.e. the whole mask may be offset by even 0.05 mm. If that happens, a trace going between pads would be exposed next to a pad, with only 0.075 mm clearance. Good luck with that, and happy debugging with malfunctioning product!
Therefore, as I and Paul said, you would need to have via-in-pad and routing in inner layer. The component package just isn’t designed for cheap simple boards.
That said, if you are really adventurous and ready to take all responsibility, you may think through carefully if some other pad is needed and take it off. The track would go under it, covered by the mask. I think you understand the risks – you have to trust blindly that the mask is good enough, and that it doesn’t have negative effect to soldering the package, etc.
You didn’t hear this “advice” from me.
That brings you to the question of the thickness of the solder mask.
This reminds me of labeling uSD cards. I once glued some paper labels (0.1mm thickness) on uSD cards, only to discover that those cards did not fit into their brackets anymore, so I had to take it off.
The silliest thing is though that this chip has plenty of pins with the same function which are just paralleled. They could have easily made this chip with a different pin order to ease the routing.
The reason why this chip is still available may be because nobody wants to use it.
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