I’m making a PCB where the electrical clearance for signals is less than the minimum via-to-via distance. I want to send all parallel signals through a row of vias. When I go to place the vias, I’m allowed to place them close (because of the short clearance for the nets), but closer than the board’s “Design Rules” say the minimum via to via spacing should be. I want to keep that higher via-to-via spacing rule.
Is there a way so that when I route the traces with vias, it forces the vias to be as far as the higher requirement between clearance and minimum via-to-via?
To put it simply, my clearance below is 3 mils, but I want to keep a 0.45mm (17 mil) via spacing. How to I set it so that routing doesn’t allow me to make the close pattern that I was able to make?
no idea if it helps, but could this solve your problem? (I think I use a newer KiCAD version than you though, so location of this feature - if available at all - will be somewhere else?)
As you can see in the UI text, the value 0.45 there isn’t via spacing, it’s hole to hole spacing. I haven’t tried but you might get the wanted effect if you calculate the needed distance between two holes of two vias. This would require having a fixed via copper ring width around the holes.
Like Joan pointed out, in v6.0RC1 it’s possible to define more complicated rules in text format (https://docs.kicad.org/master/en/pcbnew/pcbnew.html#custom_design_rules). But I’m not sure it could support your case with one simple rule. As far as I know it’s not possible to set a value to be max(A, B) or do other calculations. It should be possible to simply set minimum clearance for vias in two different nets or netclasses.
Ah, maybe I’m misreading it. I want the minimum center to center distance to be 0.45mm, whether it’s thru holes or vias. I tried testing that idea by putting a much larger minimum, 2mm, but the trace guide still lets me put vias as close as the clearance will allow. I think the behavior I’m looking for just isn’t supported maybe.
The goal is to design a PCB that works.
Designing a PCB to some arbitrarily thought up rules has no extra value. There are no “bonus points” for “making it look nice”, on the contrary. It’s bad for signal integrity.
If you have tracks that run parallel to each other for some distance, then you create crosstalk between those tracks, and that is bad for signal integrity. This can be so bad that the PCB stops working altogether.
When you have a layer change such as in your design, then also make use of it to change the order of the signals. If the vertical tracks are “A, B, C, D, E, F, G, H, I, J” then change the order of the horizontal tracks to for example “A, D, G, C, H, B, E, J, F, I”. This spreads the crosstalk among those signals, and this helps to keep it all within “tolerances”.
And for the via’s… Why do you care? Is there any real reason for it? Making PCB’s “neater” can suck up many hours of design time. The puzzle to “make it look better” does give an odd satisfaction, but it has zero effect on the quality of the end product. So to become a “better PCB designer” you have to put some resistance against this urge, and just stop caring where your via’s are. If you use KiCad’s interactive router efficiently, then tracks and via’s get shoved around all the time, and that is a good thing.
It’s not for aesthetics. I have a geometric constraint with this board and I need to pack things as close as possible. I am looking to use PCBway, where they can do 3 mil traces with 3 mil spacing for an additional fee, but their center to center hole minimum distance is still 11 mils or higher depending on how much you want to pay.
Hole to hole is most probably from hole edge to hole edge. It doesn’t say center to center! You have to calculate 11 mils = starting from the hole edge + annular ring width + copper clearance + annular ring width to the other hole edge. Center to center doesn’t even make any sense because larger holes would overlap. The idea is that a small drill bit will break if it hits another hole partly, or the thin wall between two holes will break.
I think it can be done with making “custom rules” in KiCad V6.0.0.rc1 but I’m not sure of it.
Another workaround may be to make your via’s bigger during PCB design, and then replace them with smaller via’s just before you generate the Gerber files, but this is probably not needed or even nonsence. The 11mil “hole to hole” distance is very likely from the edge of one hole to the edge of the next hole. So if you setup your rules in KiCad V5.1.x to use 3mil clearance and 4mil annular ring width for the via’s (Calculated from via size and via drill), then 2*4+3 = 11mil.
On a broader sense. Pcbway does not like PCB’s with these minimum clearance rules and clearly state that it drives up the costs. Going to a 4 layer PCB is very likely a much better. On dense two layer PCB’s it is very difficult to make a decent GND plane (I see none of it on your PCB screenshot). If the cost for a 4-layer PCB is acceptable, then this almost always is a much better option. 4-layer PCB’s are much easier to layout with a good GND plane. It is even common for lots of people to always design 4 layer PCB’s because the time saved in designing the PCB is more important to them than the extra cost of the PCB itself. Especially if you make PCB’s for commercial products and you have to conform to EMC rules.
Thanks everyone. In retrospect, yes the requirement is edge-to-edge. Without going into the nightly builds, the workaround of using an artificially large annular ring and then downsizing it works. This is not a commercial product, and there are some thermal considerations as to why this needs to be a 2 layer board. I didn’t mean that each via needs to be in a line, staggering works as well, but I just wanted to express I want to pack them as closely as possible.
