In my case, I use pin header, but I know it’s a single case, and it needs to be set…
An example would be to put an arduino-like on a mother card, you have to make the footprint of your arduino-like card, and what you have is the PCB you did, so a script to make a footprint from the PCB would be great to place it on new mother boards.
In my case, I want to create many function on a 'template" cards, and plug it on my main card the version I need (it could be differents buck-boost supply, card to read contacts or a card to set contacts, differents sensors with same communication pins, but without same physical implantation of these pins…)
I don’t know if the best way is to set an array of connector’s type to keep in footprint and ignore everything else in beginning of a script, or set a propriety in eeschema on connectors you want to keep in footprint, so the script could identify in PCB with footprint to convert in new one…
Don’t you just make the daughterboard use some easy and well known connector placement? e.g. two 5x1 0.1" headers, separated by 1".
The Arduino layout is almost a simple DIP, apart from their snafu with non 0.1" spacing.
My goal is to use pin headers with 0.1" with right distance so I can plug it on prototype card, but there is no standards of dimensions, number of pins… etc
I can use 4x1, 4x2 (not compatible with pototype card), 7x1 and so on… Connectors in parallele, but not always (not compatible with pototype card)
I don’t want to be constrained in the way I route the card, so I wonder if it’s possible to automated the way to create a new footprint from any card.
I made a little progress on a script., so far I have extracted some info from the PCB:
>>>execfile ("C:\Python_progs\pcb_to_footprint\pcb_to_footprint\pcb_to_footprint.py")
Found project c:\temp2\smart_rgb_led_at85\rgb_led
Found pcb: c:\temp2\smart_rgb_led_at85\rgb_led.kicad_pcb
edge at (91440000, 99060000) - (91440000, 99060000)
edge at (91440000, 83820000) - (91440000, 83820000)
edge at (76200000, 83820000) - (76200000, 83820000)
edge at (76200000, 99060000) - (76200000, 99060000)
origin 76200000, 83820000
bbox (76149999, 83769999) (15340002, 15340002)
P1 CONN_A
pad 1 at 1270000,1270000
pad 2 at 1270000,3810000
pad 3 at 1270000,6350000
pad 4 at 1270000,8890000
pad 5 at 1270000,11430000
pad 6 at 1270000,13970000
The next step is to figure out how to create a footprint module.
Yes, I have been looking at that. Here is a what I have now:
Original PCB
Converted to module :
The pads are numbered in the order they appear.
Very nice ! it’s what I’m looking for, for personnal development or even for PCB open-source you can find on ghitub or else, it will be faster to build footprint and include them in our project !
Hi bobc !
Is it possible to have a link to your script ?
Sure, it’s only half finished. You will also need https://github.com/pointhi/kicad-footprint-generator and edit the script a bit to point to the right path, and add parameters specific to your design.
pcb_to_footprint.py (13.2 KB)
Thank you ! I will give it a try as soon as I can.
I tried it and it works well, thank you !
In the same way, is there some script to build a 3D model from the 3D view in pcbnew to apply on our new footprint ?
Kicad stepup (assuming you have step files for the parts you want to have visible.)
Simply import the whole pcb into freecad that way, remove what you don’t need, union all remaining parts. Import the footprint you created and align the unioned 3d model to it. Export the unioned 3d model to both wrl and step.
This workflow will not include silk or copper layers of the board. If you want that you will need to export the pcb to wrl directly from pcb_new and use blender or wings to edit your 3d model if necessary. (This workflow does not allow colaboration with mechanical engineering cad tools as it does not create a valid step file.)
Thank you for your fast reply ! I will try your method.
Hi @bobc, you mentioned the script was “half finished”. Did you get around to completing the script?
Hi bobc,
would it be difficult to automatically re-use the delimiter zone of the connectors as delimiter zone for the new board since the new board will be superposed to another one and we can populate the surface under the new board, apart from the connectors ?
Thank you !
Hi, this looks interesting and useful, though a noticed some difficulties setting up the python script environment.
Pcb_to_foorprint.py activates but execution stops at missing command
Files\KiCad_5.1.2-2\x08in’, ‘C:\Program Files\KiCad_5.1.2-2\lib\python2.7\site-packages’, ‘C:\kicad-footprint-generator’, ‘C:\Program Files\KiCad_5.1.2-2\x08in’, ‘C:\Program Files\KiCad_5.1.2-2\lib\python2.7\site-packages’]
Traceback (most recent call last):
File “”, line 1, in
File “C:\kicad-footprint-generator\pcb_to_footprint.py”, line 51, in
from KicadModTree import *
ImportError: No module named KicadModTree
So this looks bit complex now, as the role of the KicadMod_Tree is
not included to search path or active in libraries known or in use?
Br
You will also need https://github.com/pointhi/kicad-footprint-generator and edit the script a bit to point to the right path, and add parameters specific to your design.KicadModTree https://github.com/pointhi/kicad-footprint-generator
Ok, this kicad-footprint-generator looks external library package to Kicad internal python environment, and the brief documentation shows how this package is installed to linux.
Now the external package installation document for the windows is not shown ? I thing there is something somewhere.
Actually this hierarchical pcd workflow could be part of the KiCad itself to add more flexibility to sch-pcb workflow phases by allowing a project to contain several pcb-designs, as long they use unique external interfaces or the signals can be manually connected.
This probably doesn’t work at trace-level, but signalling must be higher level, connector layer signal interfaces to and from a black-box.
Currently interface signalling is inherited from one schematic only, one to one relation, but some cases there can be need for pcb design include another ready made, non-standard pcb-unit as a component.
This is however not the same when sch -> pcb is many to one relation, which is usually the case used in hierachy designs.
This same result would be possible if pcb-component .cmp layer could import ready pcb-design as a source for creating new pcb component.
Signal names, pin positions and types were ready, without those trace layers that are not needed at component level.
Reusing previous pcb designs is also cost and time effective when available in the same way as with other software packages.
Br