Is there a change to V6's clearance rules?

[jtw_11]

Hi all,

I recently switched to V6, and converted what was a nearly finished large project to V6. However, I’m fighting what appears to be either a change to my board setup in V6 that I don’t understand/am not aware of, or a change to the V6 router altogether.

I have many signals broken out of fine pitch TQFP packages, into staggered vias that were all laid out in V5. 0.2mm traces, 0.15mm clearance and 0.15mm min trace width.

As you can see in the images below, the traces A7 and A9 are line for line (down to 0.01mm) on the clearance zone around their via annular rings.

However, if I delete one of these - I cannot reinsert it, the router stops me short as if there’s some clearance violation that isn’t there. If I put the trace in as 0.1mm, then change it to 0.2mm afterwards, the DRC doesn’t complain… so there isn’t a violation there.

What gives, what’s stopping me routing signals that were previously fine to route?

Interestingly, if I reduce global min clearance, and default net clearance to 0.1mm from 0.15mm, I still can’t route a 0.2mm trace between the vias.

[jtw_11]

This perhaps shows it clearer - if I put the router in highlight mode, and try to route a new trace to A9’s via, A8’s via is highlighted green, despite not being in violation.

Even if I make A8’s via some entirely impractical OAR size, such that it’s so clearly out of A9’s traee clearance zone, I still have the problem…

[jtw_11]

I have just opened an old, unfinished archived version of the project in V5 too - and can confirm I can happily route between these vias with the same trace and via sizes…

[jtw_11]

I have also tried putting the router into highlight mode, and allowing DRC violations. This lets the router route the trace (whilst warning about the 2 adjacent vias). But then DRC checker does NOT report any violations, because there isn’t one - yet the router in walkaround mode still won’t let me place the trace where it used to let me.

I’ve also just update 6.0.4 to 6.0.5 with no change.

[mf_ibfeew]

Have you tried to reduce the copper<->hole clearance?

[paulvdh]

What are the settings for the Via’s?

I normally complete this issue by never using design rules that add up to the pad pitch of IC’s, and I also don’t make rows of closely packed via’s. I’d rather have a few small holes in a GND plane then a long slot made by closely packed via’s.

When the interactive router is in shove mode, it should also push the other via’s aside to make room for a track in between if it’s needed.

[twl]

It’s very likely an issue with the via hole clearance. Could you share the PCB design from the screenshots you posted?

Thx,
Tom

[paulvdh]

Lot’s of people do not like sharing their designs.
As an alternative:

1. Make a copy of your project.
2. Delete all IC’s from the schematic.
3. Put a generic connector at the location of your QFP IC.
4. Assign it the same QFP footprint.
5. Repeat for the “other end” of the wires, so a complete netlist is generated.
6. Remove all other stuff from the schematic (it just distracts from this issue).
7. Save it.
8. Give those two connectors the same RefDes as the IC’s had.
9. Schematic Editor / Tools / Update PCB from Schematic [F8]
10. Delete everything from the PCB except those two IC’s and the 5 or so tracks.
11. Save it, exit KiCad.
12. Delete the backup directory, gerber files, etc.
13. Zip the remaining parts of the project to keep it together.
14. The result is probably 50kiB, or smaller, post it here.

[jtw_11]

This is it! The copper to hole clearance was set larger than the edge of the track, to the edge of the via holes (set to 0.275mm).

I opened the old V5 backup of the project, and cannot find the copper to hole clearance rule - it looks like this was newly introduced in V6? Perhaps 0.275 was the default clearance for this new rule option? It doesn’t appear in the 6.0.0 release notes as far as I can see.

0.275 is far above the min trace clearances etc in this board design, nor is it my fab’s rule.

Thanks very much indeed for your help!