This footprint is generating this error. Should i ignore the DRC error? Is it supposed to be like that?
The footprint is in the KiCad lib and is called Connector_Coaxial:U.FL_Hirose_U.FL-R-SMT-1_Vertical
Thanks in advance !
You have applied a solder mask expansion to this footprint hence the error messages.
No it was allready like that. i didnt apply the solder mask expansion.
Its not already like that on my system . . . open up the footprint from the library, not from your board, and you should see no expansion.
Do you have an expansion set in the Board Setup ?
see it like that from the lib. And yes i have solder mask expansion set to 0.038 mm (JLCPCB’s capabilities)
I would create an exception for this DRC violation. I don’t see a problem with it. I would probably make the aperture mask bigger, so I’m sure it overlaps the pads and it does not leave a sliver of soldermask on the insides of the pads. Very thin slivers of solder mask can break off and cause production problems elsewhere.
Oh so the pads are supposed to connect to the middle area. Thanks !
Uhm, no. The intention of the aperture mask in the center is probably to prevent the soldermask from lifting the footprint. There probably should be only bare PCB under the footprint. No copper nor solder mask nor silkscreen. But I’m guessing from what I see on the screenshot. If you want to be sure, then look at the datasheet of this connector. It often has recommendations for things like this.
But if i put F.mask on an area, wont that area have exposed copper?
Soldermask is ineed a negative layer. There will be holes in the soldermaks where objects are drawn. But it does not always have to be copper under it. It can also expose the bare FR4 (or other base material).
I was just adjusting this type of footprint in my next design, so had the datasheets handy.
I’m 99% sure that that keepout is for metal on the top layer, not for solder mask.
you don’t want signals or even ground fill in that area as the center pin metal is exposed on the back of the connector.
you can see that exposed metal for the signal pin here…
Hirose isn’t very precise on where the keepout is in their doc (I didn’t look at the altium FP)
But the same part from TE shows the copper keepout a little more precise.
also don’t forget to keep the same stackup all the way underneath the part so that the 50ohm impedance is matched the whole way.
I agree with that. However, after loading the footprint in the footprint editor, the center rectangle is definitely a rectangle on the F.Mask layer.
I’m suspecting this is an error / oversight in this footprint, but I’m not sure enough to report it on gitlab.
If get it manufactored at fx JLCPCB, will the F.mask area have exposed copper or is there another layer underneath the soldermask?
I have used this U.FL in KiCad (version 5 or 6 I guess) without problems (roughly 500 boards) and without modifications. I no longer have access to the KiCad-files (done that at work), so I can’t check.
That depends on your design. I’m pretty sure if you used the library part, there won’t be any copper under the part, there also won’t be any solder-mask. as long as you didn’t put a via or other trace under there, it should be ok. but i would delete the solder-mask opening for the next version.
@paulvdh - yes, it looks like the library part should not include the solder-mask keep-out.
If you don’t put copper there, there will be no copper, just the raw usually yellowish PCB material.