I am daisy chaining a number of buses (don’t worry - they are controlled via a MCU to stop multiple signals hitting the bus line at the same time).
Is this an ok approach to connecting the lines together? This shows red traces on the top layer, green on the bottom layer, with vias connecting each FSTD16211 chip on the top layer to the bus traces on the bottom layer. I will in the end have 4 FSTD16211(A1 - A4) chips in the daisy chain, but for representation I only show 2 here. I propose to use the same approach continuing to the right:
It has been standard way of doing PCB’s for decades, to put horizontal tracks on one layer and vertical tracks on another layer, because it is a very senisble and easy way to have multiple chips connected in parallel without getting into trouble with the connections.
With modern high speed logic however, the lengt hof the tracks is becoming ever more important, and length matching of the tracks is not an option, but mandatory to get a working PCB layout.
(I have not looked at the datasheet of your FSTD… chip)
One more note: Those tracks laying parallel to each other over long distances increase capacative coupling between the tracks, which is not ideal. You can improve this layout by adding some “randomness” into the design. For example, the length of the green tracks is pretty much fixed, but you can connect the red tracks in a different order then the green tracks. This will also prevent the via’s from all ligning up in a single diagonal line. For example, instead of putting the via’s in a single big diagonal, put them staggered on 4 or 5 slanted lines. This makes the distance in which 2 tracks are near each other shorter, which reduces capacitive coupling. Capacitive coupling between any 2 ajacent tracks can be further reduced by making use of the red “splits” to the middle 2 IC’s to change the (netlist) order of the Green tracks between the left and right side of the board.
Also for less work, do not make use of the 45 degree ends in the beginning. It’s easier to just make 90 degree bends and then later shove the tracks a bit around with the Interactive Router.
IC’s and the red tracks are on the top, while Green is on the bottom of the PCB. A lot of the green tracks can be routed under the IC’s instead of next to it, wich makes the red stub tracks shorter. Ideally, (for better signal integrity and EMI reduction) each track has an continuous (Un-interrupted !) GND (or Vcc) plane on the opposite site of the board. This can be a lot of puzzling (or impossible) on a 2 layer board, but is usually easy on a 4 layer board.
Top - red signal
Layer 2 - GND
Layer 3 - VCC
Bottom - green signal
So to summarise your thoughts:
1/ Try not to have diagonals of vias - do banks of 4 or 5 on the same diagonal before changing to a slightly different starting point.
2/Use 90s where possible for simplicity
3/Route tracks under the ICs, (but I still need room for the Vias, and the edge of my board is just under the bottom edge of my pic)
Can you clarify what you mean by:
Capacitive coupling between any 2 ajacent tracks can be further reduced by making use of the red “splits” to the middle 2 IC’s to change the (netlist) order of the Green tracks between the left and right side of the board.
Also – do you have a tip of making long traces absolutely straight? I find it very hard to make sure the traces are running in a completely straight line!
Also, the 45 degree slans are motly easthetic and do not matter for the electric functionality.
When two conductors are near each other ( Whether on a PCB or in a cable) they form a capacitor. In fact, any capacitor is 2 pieces of conductive material with an isolator between them. Capacitors (even small capacitors) tend to be a low impedance (and thus conductive) for high requencies. The capacitance between long tracks can be high enough to cause glitches on an adjacent track during the flanks of on the signals on another track. The goal is to reduce this capacitance, so the coupling is small enough to not cause glitches in logic signals.
The capacitance of a capacitor is dependent on:
The dielectric (which is pretty much fixed for you).
The distance between the conductors (= distance between tracks).
Area of the conductor (= translates to length of the tracks.)
If you look at the leftmost track on your screenshot, then first 2 parallell red conducors go from south to north, then in green they go from west to east, and then they go from north to south to the next IC. The capacitance of all this length of these tracks is added to each other. If you turn the single line of diagonal vias to 4 staggered lines, you disrupt this patern. The leftmost track still goes from south to north, but the south to north connection is parallel to another wire then the green West to East connection. As a result the capacitance between adjacent tracks is devided over several nets.
In your situation:
A + B = South to North.
A + B = West to East.
A + B = North to South.
What you want is:
A + B = South to North.
A + C = West to East.
A + D = North to south.
B, C, D are all different tracks. So when track A switches, it will cause a small disturbance on tracks B, C and D, but none of these distrurbances are big enough to cause a glitch on any of these signals. However, if tracks A and B are next to each other from the left IC all the way to the right IC, the capacitance between these tracks is bigger and may be enough to cause a glitch on the ajacent track during a 0->1 or 1->0 change on the signal.
Start at the long line instead of the pad. Or ensure that your long line is on grid. (one easy way to guarantee this is to set the grid origin at one endpoint of it. Made much easier with the snap to anything feature added to 5.1)
I think your advice is probably valid regardless, and I have focused on power and analog more than high speed digital. However, in about 1978 I performed a test with an 18 inch long test board. It had two straight narrow traces spaced close together. I drove one trace with a (few nSec) long pulse which I generated using a transistor avalanche circuit. I could observe line reflections and coupling effects. One thing that I learned is that for low voltage circuits, it seems that inductive coupling is a much greater concern than capacitive coupling. By varying the connections and loading on the two traces and by observing the polarity of the induced glitch, this point was fairly clear. Once in my life I encountered what was definitely capacitive coupling. I had a rapid edge about 40V close to a sensitive comparator input.
The other thing at play here is that input capacitance of a typical input gate is relatively high compared to trace capacitance, so while you will observe the capacitative coupling on the trace and fast edges the chance of it causing side effects is quite low until you get to very fast sensitive (i.e. low capacitance ) stages like those for high frequency signals. But if you are unlucky and the coupled impulse is very close to a “real” transition, it may cause glitches