Is there a way either extant or planned to specify differing clearance between nets within a netclass than for those outside of it. This is often useful for ensuring that DRC and fills maintain proper clearance for high voltage nets while allowing tight routing within circuitry that is all at nearly the same voltage. For example if you have a line-powered converter there is often a lower-rail which has gate drivers and resistive current sensing, a set of nets for the switching node which has a gate driver (15V away) and a high-voltage DC link that is 400V away from the lower rail.
What I’m wondering is does KiCAD have any support for this kind of design rule yet or must it be done manually?