I've written a tool to generate an eeschema symbol library from the Quartus Prime Pin assignments.
When you run the Quartus fitter it will produce a .pin file in output_files/ in your Quartus Project directory.
Running './qpin2lib.py my_proj/output_files/my_proj.pin >my_proj.lib' will produce a symbol broken down into sub-symbols for each IOBANK, JTAG, Power, and Unknown (the stuff I haven't categorised yet). The subsymbol is sized to contain the
number of nets in the subsymbol and the length of the longest net name, and annotated with the pin assignments for each net.
It's still not as great as the FPGA integration in some of the commercial Schematic/Layout packages, but it's a huge improvement over trying to manually create symbols for your FPGA (mine has 672 pins!)
Anyway you can grab it from here: https://github.com/puddingpimp/qpin2lib
There are still a few things to improve on it:
- Make the Power symbol a horizontal symbol
- Automatically annotate the correct footprint for the package
- Sort the signals on each symbol once I figure out what the correct sort is
I just hope it helps someone, it's certainly helped me.