I hereby certify that I am not simply asking someone else to design a footprint for me.
This is an auto-generated message that is in place on the “footprints” section of the KiCad.info forum. If I remove it and ask for a footprint to be designed anyway, I understand that I will be subject to forum members telling me to go design my own footprint or referring me to a 3rd party footprint site.
Hi all, I’m working on a footprint for an RF connector on a 4 layer board. I have done FEM simulations to design the footprint and now I’m trying to implement it in KiCAD. The footprint should look like this:
That is, it should have a centre via with a pad on top and then clearance rings around in all layers. The clearance rings should have the same radius in all layers. However, I do not manage to do this in KiCAD. I cannot do anything on the inner layers in the footprint, so I have done this by filling a zone in the layout. However, it does not with the same radius in all layer, and I cannot find any setting to get this. Any suggestions? This is how it looks now:
Questions
Second picture, top & bottom layer there is space from copper in pad1 to ground that is correct but the inter layers that space is too small?
Have you done a area fill in all four layers? (the “filled zone” is outside the foot print)?
How do you see this? Looking at the gerber files?
Correct, the top and bottom layers space from copper in pad1 to ground is correct. However, I think this is since I have a pad in the footprint in these layers that defines the distance. I cannot make a pad in inner layers in the footprint, and thus I used filled copper planes in the layout. These fill too much and it can be seen directly in picture two above. The yellow ring inside the red around pad 1 is from first inner layer, and should not be closer to the via center then the red (layer 1). I have not looked at gerber files.
Not sure what you mean that the filled zone is outside the footprint.
By the way, here is the footprint as it looks now. footprint.zip (1.6 KB)
Thanks for the .zip. Have not look at it yet but that usually really helps.
When I edit a pad this window pops up. It appears to me that you have a choice of where copper is applied. “all layers, top only, bottom only, no layers…” What do you have that set to?
If I understand correctly, the pad clearance is for the pad, but I want to control the clearance to the via in the inner layers. I don’t think I can change it there. The via is only connected to F.Cu and B.Cu which is the way it should be.
I would have expected this setting to do the trick, but it does not
It urns out I do not know how to open a foot print that I just down loaded. lol
Here is a picture of the board I am working on. There are some real high voltages on the board. Red=top and Purple=L3. I need clearance on all layers from the HV signal. On the left side there are some capacitor leg holes where the Red layer stays away from the leg and the L3 layer connects to the part. On the right side there are some areas where all layers stay back from the signal.
There are several ways to do this. Some time I go into a part and say that this pin will need clearance any time I use it. So I set the clearance within the foot print.
Many time I leave the part alone. During layout I see this pin needs clearance so I select the pin (not the whole part) just the thing I want isolated and set the clearance to 3mm or some thing large.
This is a scope probe holder. It might be used to see 700 volts but in this case it is only looking at 12V. On the part I set the center pin clearance to 3.7mm. The other 4 pins are set to default. There is a yellow circle that shows the clearance.
Going back and looking at the parts it appears I some times set the clearance with in the part and some time add it in the layout stage. Either way I have not touched the Fill Zone numbers. (not really true see below)
I noticed in some cases I change the property of a “net”. So I have “+supply” set to have a clearance of 3mm. (1500Volts) This adds that to all copper related to that net. So the third way of getting clearance is to set it by the net name.
RonS.
I do not know. On my board you can clearly see the fill zones back away from the pads. Through hole and SMD devices and vias. And the fill zones back away from traces labeled high voltage.
Some of my fill zones are high voltage and so the zone backs away from everything.
You didn’t tell you are using 5.99 (which can be seen in the zone dialog screenshot). That’s important because it has a new DRC engine which may very well have bugs. If your version is up to date and you have found a bug, please report it.
On the other hand 5.99 has a rule definition language with which you should be able to set clearances for almost anything.
There’s also a hack which may help. It’s possible to open the footprint in a text editor and change a SMD pad’s layer to for example In1.Cu. It actually works, but there’s no UI to do that.
In the screenshot I have done that for one of your custom shaped pads, it’s in In1.Cu layer.
Ah indeed.
There are lots of changes between KiCad V5.1.x and KiCad-nightly V5.99.
One of the changes is that in V5 all pads have the same shape on all layers, while in V5.99 a first step has been made to implement a “full pad stack”. Currently you have the choice to draw pads on all layers, or to tun the pads off for layers on which there is no track connected to the pad.
This is a property of a THT pad. You can set this by selecting a pad (either in Pcbnew, or in the footprint editor) In V5.99 you can set the “Copper layers” property of a pad to either:
All Copper Layers.
F.Cu, B.Cu and connected layers.
Connected layers only.
None.
My dialog for pad properties in V5.99 (Fresh install yesterday) looks quite different from ronsimpson’s:
I guess his nightly is several months old at the least.
I am also confused by the screenshots in your first post.
The first (green) screenshot shows a pad with 8 GND via’s around it.
The second ( KiCad Red) screenshot also shows 4 red circles. and 4x a big “GND” text. What are those?
Have you experimented with KiCad’s 3D viewer? (I guess not).
It is an excellent way to look at what is really inside the PCB.
To do this:
[Alt + 3] to start the 3D viewer from within Pcbnew.
Rotate the PCB a bit, so you have a 3D view.
3D viewer / Preferences / Display Options
Turn off the checkbox for [ ] Show solder mask layers.
Turn off the checkbox for [ ] Show board Body.
You have lots of GND zones, but if you turn those off to, you don’t see them anymore … You can opt to make a small test PCB, or temporarily add a “rule area” to the PCB (this was called Keepout Area in V5.1.x) to see through it.
Thanks, @eelik, that was nice. I actually tried that on 5.1 and failed, so very nice to know they added that. I tried it, but unfortunately, it does not solve the problem. The copper layers on In1.Cu and In2.Cu still fill too close to the via:
I think I will submit this as a bug or a feature request, bot sure. To me, it seems there is one option missing to set this clearance. I don’t know where KiCAD gets the actual clearance value used from.
Now I actually solved it. I increased the pad clearance on the center pad. That makes the clearance wrong on F.Cu and B.Cu, but it does not matter since that is solved by the circular pads in the footprint. It looks like that clearance number is used for two things, both clearance to the pad and clearance to the via in the inner layers. This is probably fins from a manufacturing and DC standpoint where the clearance is important for lithography line-width and discharge in e.g. high voltage applications. However, for RF you need to be able to control these properties to greater detail. But the trick of adding inner pads manually in the footprint solves it so thanks!
KiCad is quite finicky about that.
It only sees footprints that are in a library, and if that library is also added to the library table. If you have a project with a custom library (A directory ending in “.pretty”, then you can move the footprint into there, and it is visible in the project.
@ravn
After viewing & dissecting the footprint in KiCad I finally understand the extra clearance lines.
They are overlapping clearance circles from the SMT pads you added. But why did you add SMT pads to this footprint? The GND zone keeps it’s clearance normally from pin 1.
By just deleting all 8 SMT pads from the footprint, it still looks very much the same as in your screenshot. Here I put it on a 4 layer PCB:
Inclusive the apparently faulty clearance for the inner layers.
However, when looking at it in the 3D viewer (and disabling solder mask and Board Body) it looks like:
As you can see, the pads are removed from the inner layers of pad1, and according to your description this is not what you want.
So I selected the center pad in Pcbnew, pressed e to edit it’s properties and changed: to:
This makes the clearance holes in Pcbnew the same size and also shows the rings around pad 1 in the 3D viewer:
Is this what you want?
Your first (Green) screenshot does not show any zones, and the proportions are different (I did not change them)
In case you want to exchange further data:
Please do not call a footprint “footprint”. (Nor call projects “test” or other generic names. There are too many of those. (I once gave my laptop the hostname “laptop”, it seemed sensible to me, until I went to a meeting and turned on WiFi.)
Clearances are normally set by the net classes & design rules for pads and tracks. You can however specify a clearance in a pad, and if you do so, that clearance overrules the clearance of the netclass (if it is bigger).
If you have troubles with clearances with zones on different layers, you always have the option to use different zones for each layer, and control the clearance for each layer separately.
Thanks for the reply. I am sorry, I did not manage to explain properly. For the center via, I want pads on F.Cu and B.Cu, but not in In1.Cu or In2.Cu. However, the radius of the clearance zone on the fills should be the same in all layers. The important property is the distance between the via wall and the surrounding metal. Using the solution I described above solved all my issues. However, I can imagine still that this could be improved in KiCad by allowing different clearance between the pad and the via. For RF applications I think you will almost always implement this in footprints as I did now, and then it is probably not a crusical improvement since there is a working solution.
There may be still one possible alternative solution. In 5.99 you can have rule areas, i.e. keepout zones, in footprints. You can create a circular keepout zone by creating a graphic circle:
Then use context menu -> Convert -> to Rule Area. It creates a cicular area approximated as a polygon.
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