I have noticed that I have nets traveling over keepouts. When I review why this is, I notice that my metal layer keepout diameters are different depending on what the via is. My signal via keepout size is what I want and my ground and power vias are larger. I have tried to remedy this by changing the parameters in the board setup as well as the copper properties on a metal layer. Nothing helps.
The one thing that I have noticed making a difference is how I specify the annular ring in the via settings. If I set the annular ring property to connect at all copper layers (default), the keepout size is large. This is how my ground and power vias are defined. My high speed net vias are set to connected layers only. This gives me the keepout size I want.
I can change my ground and power via properties to connecting layers only and this works. I think that regardless of my via setting, the keepouts should always be the same diameter. What am I missing?
There are a few things confusing here. First your usage of the word “keepout”. If I mentally replace that with “clearance” your post makes more sense to me. Next is the colors. This is a multi- layer PCB and you probably have disabled a bunch of layers.
From this description:
I get the idea that you may not completely understand what this does. In your screenshot I measure nearly the same clearance distance for all via’s. (somewhere between 36 and 38 pixels on your zoom level). The only change is that this clearance moves outward if the via has an annular ring. The 2D rendering of multiple layers can be confusing. You get a clearer picture if you view your PCB in the 3D viewer [Alt + 3] Then also disable the Board Body and the solder mask F.Mask and B.Mask layers in the appearance manager on the right.
Also, changing via’s does not change tracks. If you for example make a via larger, then the clearance to other copper items around id becomes smaller. Very likely this creates DRC violations, but you do not know that until you run DRC.
Claudio, thanks for your input. You were correct that I had a parameter in my power net-class that was not consistent with my other net-classes. I believe it was the DP Width or the DP Gap. In either case it shouldn’t have mattered as none of my power are differential (just through hole). I still made the change for consistency sake and redrew the metal fills. All power vias remained at 40 mil diameter, whereas the nets are 30 mil diameter.
Paulvdh, thank you for your feedback. You are correct that I use the word keepout instead of clearance. You are also correct about the multi-layer PCB (18 to be exact). I am only displaying two layers in the pic. One is a power layer and the other is the adjacent net layer (a requirement for DDR4).
While I believe I have a good understanding of how the annular ring options work and how they are represented in my PCB viewer, maybe I don’t.
I am trying to have a mix of annular ring configurations. One for all high-speed nets and another for power layers. My net via “clearance” diameter is 30 mil, while my ground and other power via clearances is 40 mil. I want all my via clearances to be 30 mil. With this reduced diameter, my nets will not pass over an adjacent layer clearance.
I have used the 3D viewer in the past, but never at inner layer levels, so I’ll give that a try and see how it compares to the 2D view.
Clearance is copper-copper distance. You are using it in different meaning.
I have written post about - why at PCB with so precision tracks (4 mils) you use so big clearance (30 mils). And than found that all I have written is only suitable for removal.
For clearance, the outer edge of the via is the same as the edge of the track. There is probably no point in distinguishing clearance for via as any other.
Claudio, you were correct on the net-class configuration parameters. I had a conflict with some net-class distance settings that were 7.87 mil. This conflicted with my constraints setting for copper to hole clearance. I was able to then set the various copper zone distances to what I wanted. Things look better now.
