Impedance discontinuity vs void clipping

Hi Guys,

I wanted to share this to get some opinions (or facts if possible) as to what is the best compromise.

I am routing some high speed 100 ohm differential pairs and trying to escape a connector.
These signals could be running at 10gbit/s

Due to some constraints (track/space) being driven by the stackup and the need for backdrilling and keeping the via count down I have a track width of 100um and a space of 210um.

In addition because the of the high speed traces and the need for anti-pads around the via transitions currently set to 150um greater than copper means I am left with a couple of interesting choices.

Below is an example image. with the top diff pair using the track/space settings specified above.
Note that the diff pair clips the anti-pad voids by 20um on each side trying to escape the connector.

I have 3 choices the way I see it.

  1. Accept the void clipping as it escapes the connector and take the hit that the referencing won’t be as good and will impact the signal integrity.
  2. Neck the spacing down to ensure continuous reference but have an impedance discontinuity for a short period, also affecting the signal integrity
  3. Go back to the drawing board on the stack-up to find a way to reduce the pre-preg/core thicknesses enabling thinner track/spacing for the diff pair.

If I had to guess I would think that option 2 would be the best option and take the impedance discontinuity on the chin on the basis that skew matching also causes impedance discontinuities but is a necessary and accepted practise.

Curious to see what you guys would recommend.

Considering that layer-to-layer registration tolerances are generally ±50micron, you are not guaranteed that any of your trace are fully covered.

But you will want to consider why you think that is important. The purpose of a reference plane is to provide a fixed impedance path for the induced current from your voltage transitions. So, you want to know the difference in impedance for an embedded microstrip that is directly under your plane vs the impedance for a strip that is also directly under a plane but the plane is slightly further away. How much further? There you will need to use your Pythagorean formula to calculate the nearest distance to the plane (sqrt( H^2 + (20um + 50um)^2)) in the worst case. Plug those two values into an embedded microstrip calc and compare. If it is within your tolerance, you are golden.

However, just moving the traces closer together is not going to guarantee they are fully covered. And your impedance difference is likely to be larger moving them closer together than it is just allowing them to be the same distance further from the ground plane.

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Hi Seth,

Appreciate the reply. There will be no reference at that void XY point because the anti-pad goes through the whole stack as its a through via.

I might be able to change that and reduce it a bit, but not by much as I still need to account for the backdrill clearance.

I hadn’t appreciated the 50um registration tolderance. I looked at the specs for the MFG I’m talking to and its specified as layer to layer positional accuracy of +/-125um.

I’ve fired off a couple of questions to the MFG to see what they say.

Just to share in case anyone else might face this type of problem.
I’m now considering to accept an slightly bigger via stub on the back drills that were driving the cores to be bigger and hence the increase track/gap settings.
Via stub may end up being 6mil instead of 2mil, but thats still pretty small.

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Can you put one trace on top and the second directly below it (adjusting width to get Z based on prepreg thickness/Er)? Then ground below that (core thickness away).

edit: The ±50micron reg tolerance Seth mentioned probably makes this unworkable. Just thinking out loud.

I thought that was bad practise to run diff pairs on different layers e.g p on top and n on bottom.
Specially as then it damages the symmetry of the diff pair going through the via.

References are three-dimensional, even if we typically simplify them to 2D for our calculations. Even though the edge of the track is not directly beneath your plane, the mutual inductance still exists between them. It is just a touch longer distance.

That said, you will definitely have edging effects, whether or not you are directly beneath the plane. Our simplified assumptions for non-simulated calculations require there to be an infinite surface. This only works when the divergence from that model is minor relative to the first-order effects. But right on the edge, you already have lost half of your return path (where the anti-pad is). Shifting that a few microns one way or another is not going to materially affect it.

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Is there a reason your ground plane does not fill the interior regions?

Thanks Seth makes sense, sounds like the best option is to suck up the slight clipping.

Yes teletype, its to try to keep the impedance of the differential pair matched as it transitions thought the via to reduce the impedance discontinuity effect.

I have not done a diif pair at these speeds, so not my area, but what if gnd was allowed to bump down part way to minimize missing ref, yet stays away from the vias?

its physically possible to do that, but I believe from a signal integrity point of view it would like cause a bigger issue with the lack of oval antipad on the pair that you are trying to solve with the reference plane.
Only way to really tell I think is going through the high speed simulation with something like Ansys HFSS or getting it made and testing it.

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That transmission line does not look right to me. A much larger spacing between the pair than to the adjacent plane and presumably to the plain beneath. I think that the two traces will behave more like separate coplanar waveguides with ground plane.

Why don’t you connect your signals directly to the connector pin? The way it is now you have a via and then the stub from the connector. So why the via? It would solve all of your issues if I am not mistaken. Besides that what @davidsrsb said, with so much space between the traces there is not much coupling going on.

Ok, so the via spacing comment may be correct, I picked the match the via spacing to the same as the pre-fit through hole connector pin spacing. I’m not sure what the via spacing for the differential pair should be. If you have any recommendations on that it would be helpful.

As for the reason as to why use a via and not just connect the signal directly to the pin it is because the orange traces are on layer 3 so quite high up in the stack, and I would be unable to backdrill the pre-fit pin hole from layer 14 up to layer 3 because the pre-fit pin wouldn’t make contact any more.

So to remove the stub from the pin the approach is to do a a u-turn via where you take the signal down to the bottom of the stack and then connect it to the pre-fit connector pin hole. We’ve used this method before and had it simulated with products like HFSS and its better to have the u-turn via that keep the pre-fit pin stub.

The via hole is 0.25mm the via pad is 0.45mm and the anti-pad is 0.15mm extra so given the via pad diameter is 0.45 and add the anti-pad extra of 2x 0.15mm gives a total antipad diameter of 0.75mm.

Maybe thinking on what David said to given the pair a bit of symmetry with the via spacing I should have the vias spaced at 0.75mm hole to hole.

Are you sure you are using the right type of connector? I do not know much about high speed design, but to me it appears to be a bit odd to use THT connectors for these signalling frequencies. Are these via’s a recommendation from the connector manufacturer?

Hi Paul, yeah they are the right connector. They are the only connector. It’s a defined connector and been used for upto 25gbps with success. Unfortunately one of the constraints of doing this type of card design is the need to use this specified connector.

Thought I’d follow up with a couple of pictures for what the routing ended up looking like.

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