For high pin count BGA semiconductors or connectors we have to address more typical problems. Even if a huge all in one symbol fits to the drawing sheet, there is hardly space to connect peripheral circuit on same page. Therefore the schematics contains an average of only one or two huge components per page. Understanding such schematic circuit becomes similar painful for humans as we would only open the resulting netlist table with a hex editor.
The STM32F107 example shows how to explode the medium size mainstream uC to fractional symbols. WordPort, BytePort,Bitport what can be very generic and mixed in the schematic in any combination as long as the forward annotation tool can cluster all to the number of components intended by the circuit designer.
This is the end of examples for V6 experimental library concept what maps everything. If you see anything else what cannot mapped comfortable by this concept, pls post datasheet link
