Crosstalk is very dependent from the physical layout of the tracks. To simulate that you will need a field solver like OpenEMS. Apparently some people have success with this in combination with KiCad / FreeCAD, but it’s probably not very “integrated” yet.
But with your transmission line you already have a very similar problem. How do you verify that your nice looking model is close enough to your PCB properties to be useful?
Crosstalk is very dependent from the physical layout of the tracks. To simulate that you will need a field solver like OpenEMS.
I just need to determine the minimum separation between long-running parallel traces. What I’m looking for is pre-layout analysis tool like Hyperlynx.
From what I can tell, OpenEMS doesn’t understand IBIS, so I would have to first generate the driver output waveforms with (now) KiCAD or some other tool that understands IBIS. I would then have to manually “draw” the trace geometry with code.
But with your transmission line you already have a very similar problem. How do you verify that your nice looking model is close enough to your PCB properties to be useful?
I no longer have access to (expensive) commercial signal integrity tools, so I guess all I can do to is measure the waveform with the modest bandwidth oscilloscope that I have. My “nice looking model” at least gives me a rough idea.
I’m currently limited in the number of consecutive thread comments, so here is the continuation of my screenshots that I couldn’t post before…
The ringing is worse without the series termination resistor, as expected.
I should have picked a higher frequency and a longer transmission line to better showcase the utility of this sort of simulation.
In my particular case, I just wanted to check if series termination resistors would be worthwhile on an SPI bus running only a few inches. Plus I wanted to check what was the slowest GPIO speed I could get away with and still have a clean-looking waveform.
Thanks again to the devs for this wonderful feature!
ngspice offers a model for coupled transmission lines. Please have a look at chapter 6.4.2 Coupled Multiconductor Line (CPL) of the ngspice manual (Ngspice, the open source Spice circuit simulator - Documentation: manual and control flow).
I can imagine that you have for example two drivers, two receivers and two coupled transmission lines.
Unfortunately the description in the manual is too short and seems to be not aligned to the example netlist lines.
However there are some examples for using the CPL transmission lines in our example distribution at TM examples.
For those wanting to model vias as very short transmission line segments, I discovered the Saturn PCB Toolkit that can calculate their impedance:
The transmission delay of vias is of course insignificant, but what may matter more is the impedance discontinuity causing reflections and degrading the signal.
This of course assumes the PCB trace references the same ground/power plane after switching layers. I don’t know how to model a change of reference plane; I don’t even know if it’s possible with lumped RLC components and transmission lines. It gets more complicated when you consider “stitching” vias/capacitors. This is why I like 6-layer PCB stackups (not considering their cost). 
Did you read my above comment?
Now, if you open two more different threads and read a total of five different posts in those threads, you will promote yourself to Basic, when you will then be able to post whatever in any volume. 
Yes, I read your above comment. I unfortunately don’t yet have anything else to discuss that’s worth opening two new threads. I’m still learning KiCAD, so I guess it won’t be long until I have some questions or suggestions. A lot of the questions I had along the way had already been answered either here or on other forums.
I suppose I should have started a new thread about my IBIS experimentation instead of hijacking this one (with my apologies to the OP).
Sorry, open means click on and read/look at a few posts.
Open doesn’t mean start new threads.
I appologise for the confusion.
Hello to all,
I’m very sorry but in the mean time I completely forget to come here and see all you’re interesting replies. Wow ! I didn’t expect that
Many thanks to Holger, because I didn’t know that Ibis model describe only the interfaces of ICs
Very interesting !
Thanks a lot again and best regards to all,
Pascal
