I need some help with routing my Bypass capacitors

I’m having an issue when routing my bypass capacitors in a situation that uses a through hole via. The situation can be seen in the screen shot below:

As you can see, I’m using bypass capacitors for the 3v3 supply on 2 pins of my ESP32 SoC. However, I need to use a via to route the signals as there is another track in the way.

My concern is that we are now reconnecting the 3v3 power plane on layer 2 after the bypass capacitors, which is providing a path for the power without going through the bypass capacitor network.

How do I solve this problem? Maybe it’s equivalent to my schematic regardless?

Do you have a ground plane? How many copper layers do you have?

General rule is to use a ground plane closely spaced under the signal plane. Also, the smaller bypass capacitors should go as close as possible to the IC because it is filtering the higher frequency current.

This is a 4 layer board with a ground and power on layers 2&3 (signals on front and back)

I can only speak assuredly for myself, but I think that most of us on the forum do not have enough information about what you are doing to figure out your routing issue. I don’t know if there are any straightforward “formulas” for getting the layout done. But one idea is to try ripping up a fair amount of what you have and re-doing it.

As a power designer, power is first in my mind and I try to hook up bypassing capacitors before anything else. Placing bypassing capacitors as an afterthought was a big error in the days of TTL logic, and that was the first thing I worked with as an engineering intern.

Another point is that often the layout can point to changes in the schematic rather than always having the schematic dictate the layout. So if your IC requires good high frequency bypassing on those two pins, I would place your smallest bypass capacitors (1 each) as close as possible to those pins. Then if you need to have a bigger one, it is probably OK if that one is slightly further away from the IC.

What is the size of that smallest bypass capacitor you show at the top of your image? I hand solder 0603’ chips pretty easily on a small 0805 footprint. I hate to use 0402s but I am guessing that small capacitor might be an 0402 or 0201 chip.

If it’s a 4-layer board, put that cap close to the power-input pins and then connect to power and ground with vias. That’s all you need - you don’t need traces to connect from the cap to the part pins.

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If so then where from you have a blue 3V3 track. I’d expect 3V3 vias being connected by power plane so no need for that track.
This small bypass capacitor should be placed as close as possible to the IC power pins. Impedance of connection between capacitors and IC is the key problem here. If I remember well 1cm track is about 1nH. If you prefer to connect bypass capacitor directly (with track on top layer) I would use 2 those small capacitors (each power pin having its own capacitor). Where the big capacitor is placed is typically not important.

Off topic, but why did you decide to go with a power plane instead of 2 groundplanes in the middle? I think 2 groundplanes is better because:

  1. The signal traces on both outer layers have the same “way” to ground.
  2. The return currents on both layers don’t have to go through decoupling capacitors.
  3. When a ground plane is “damaged” by having a trace on the middle layer, it can be repaired bi via-stitching it to the other ground plane.
  4. The power supply trace has more inductance, so together with the decoupling capacitor, the noise from one chip can not travel to the next chips as easily as through a low-inductance plane. But I’m not sure, as the power plane forms a very small capacitor with the ground plane, wich helps with the decoupling of the power. But I guess this is a very small effect, as the ground plane and the power plane are far away from each other (At lease far further apart than each signal layer is from it’s ground plane.)

My workflow is a solid groundplane, then place the small decoupling as close as possible to the processor, then any crystal and only after that the I/O and bulk decoupling.
I have passed MIL-STD EMC tests several times with this approach

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