I need help connecting a small pad to a large trace

[paulvdh]

@pietrodcs

Fix me if I am wrong.

I think I have fixed it.
I’ve made a little pet project out of this to refresh my own memory about the details involved in making such a footprint. And I think I’ve succeeded quite well. To get closer to your exact layout is possible, but will just be esthetics and have no electrical use, but if you want you can refine it further.

I’ll attach the whole project, so you can take it from here, but first I’ll show you some of the important details to get it right (and which would be hard to find for a beginner).

I started with a schematic, just to have a vehicle to make the rest.
This takes just a few minutes and is quicker then trying to work around it without a schematic.

This is the result in the 3D viewer.
The copper in the GND zones is completely defined by the clearance rules of the tracks. If you want to have the GND zone look more like your screenshot, you can define additonal boundaries for the GND zone. (I also have not added stitching via’s).

It took a few iterations between the footprint editor and Pcbnew to refine further details. In the end I used 3 pads for the signal connection.

1). A narrow pad for the soldering of the pin.

2). A bigger rectangular pad for the “wide section”.

I have also used this pad as the “attachment point” for the track. To get this attachment point far enough away from the “GND Pads” I used an offset in the pad parameters. Select the pad, press e for edit and then I added a suitable number for the “shape offset”.

For this pad (and the trapezoidal pad) I also removed the F.Paste and F.Mask layer, so only the copper remains.

3). A trapezoidal pad to get (nearly) to the width of the specified 1.74mm track.

Getting the parameters for the trapezoidal pad right is a bit finicky. (In lesser amount also for the pad with the “Shape Offset”. In KiCad pads are painted around their attachment point, and coordinates of graphics is relative to that point. In your screenshot only the edges of the pads are defined, and you have to calculate the pad center yourself.

That was most of the footprint design. I’ll get back to other details later.
After I had a somewhat usable footprint, I continued with the PCB.
After the usual stuff ( Outline on Edge.Cuts, import Footprints, Footprint placement) it’s time to set up the Net Classes. I let the GND be default, and only added a single netclass for the “Input” and “Output” nets. (By the way, this is the reason I labeled them in the schematic. Labels in Eeschema make it easier to find specific nets and assign net classes). Pcbnew / File / Board Setup / Design Rules / Net Classes I only bothered to set up the track width of 1.74mm, and the clearance of 1.5mm.

And then assigned that net class to the “Input” and “Output” nets.

Now everything ws set up for routing the tracks with this wide track and big clearance. (At least I thought so). But I missed a detail. Normally pads of a footprint inherit the clearance from the net they are attached to. For this particular project the clearance of the net is however so big that it interferes with the GND pads of this footprint.
To fix that, I went back to the footprint editor and set some fixed values in the “Local Clearance and Settings” tab. The default of zero, is interpreted as inheritance, while a number overrides that with the number entered.

The final result in Pcbnew (Including shown pad clearances) now looks like:

And the PCB passes DRC without any errors.

There are some other details I have not mentioned yet. For example I made a project specific library to hold the footprint. Footprints like to reside in libraries in KiCad. If you have questions about library management, then first read:
https://forum.kicad.info/search?q=library%20management%20in%20KiCad%20Version%205%20category%3A19

I also drew the zone boundaries outside of the PCB and in a weird shape. This is the quickest way to draw a polygon, but I did not do it out of lazyness. Some people draw the zone boundaries over the Edge.Cuts graphics, or near there, or draw the boundaries over each other. Drawing the weird shape as a few advantages.

1. If there is a problem with Edge.Cuts and the zone flood fills to that boundary it is instantly clear when generating Gerbers there is something wrong.
2. This way each zone boundary is easy to select for if you want to modify it. (Oh, forgot to mension, I set “Pad Connections” for the Top GND zone to “Solid” instead of the default “Thermal Relief”.
3. It’s quicker to draw, no fiddling with accurate coordinates.

Another small detail is that I drew the footprint 90 degrees rotated from your screenshot. According to KLC pin one must be in the upper left quadrant for each footprint, and by doing so, I stay closer to this convention.
Yet another detail is that I took the liberty to use small rounded corners for the pads. The consensus is that rounded corners in the solder stencil leads to better release of solder paste and therefore a more uniform amount of solder on the pads.

I think I’m finished now, so here is the zipped project:
2021-03-10T16:35_asdf_pietrodcs.zip (8.3 KB)

[pietrodcs]

Thank You
It is clear. I still do not see the project.
It is a very good suggestion.

My Best thank
Pietro

[pietrodcs]

Thank You
I can see the project today. My connection is not the best in the moment.

Best Regards
Pietro

[BobZ]

I agree, sort of. I like to use default trace width of about 1 mm and make it narrower only where necessary. So many of my traces have varied trace width. Often times I will adjust the width in several steps to go from 1.0 to 0.25 mm for example. I think that wider traces are almost always better except possibly where HV spacing or minimum capacitance is a concern. But with voltages < 50V I think that more copper is usually better.

[paulvdh]

You can change track with in a net, but not clearance.
The screenshot from OP specifies a clearance of 1.5mm, which is quite a lot for such a small SMT footprint.
I assumed it was for some low capacitance HF thing, but don’t know any details, but I got the example project through DRC without errors.

Another solution may have been to use net-ties and split the nets near the footprint for smaller clearance but that also has it’s drawbacks.

My solution for stacking some pads and then overriding the clearance with fixed values for the pads worked quite well. If you know another method for managing the 1.5mm clearance near these pads I’m curious to know how you’d do it.