I have a new idea about simulating the circuit, can it be implemented in the future V7?
When verifying a new design, I need to insert some parasitic components, such as resistors, capacitors, inductances, etc., into the schematic diagram of the circuit to simulate and see their impact on the real circuit. But it is not hoped that these parasitic components will be treated as real components into the layout when the PCB is made, because they do not need to appear on the PCB.
The usual practice is to delete them when the schematic is converted to PCB Layout, but I hope to keep them:
Because they can help me think about further verification and improvement of the design when completing the PCB processing, deleting them will cause me to lose some of my ideas.
If I re-improve the design, I still need the previous virtual components for verification. Adding them again, and then deleting them when layout again, is equivalent to doing extra work.
When parasitic resistance and inductance are converted into PCB, the electrical network at both ends can be directly short-circuited to ignore them. The parasitic capacitance can be discarded directly.
So, is this new idea reasonable? Can it be implemented on V7?