I cannot place vias with differential pair in a tight area

Hello guys,

I am trying to route a USB-C connector when I have to place some vias close to the pins in the Differential pair mode. However, I am not able to do that.

So, I am wondering if this is a bad configuration from my side or a bug in Kicad’s router.

If I am using a single trace, I can place vias as you can see on the placed vias. Now, I am not sure why I cannot place this pair of vias. It also shows this whiteish area around the vias kind of indicating the space required or something, but I am not understanding this too.

Do you have any idea what is going on here or what I can do to check or improve this behavior?

Also, if I change DP via/hole rules, the whitewashing area seems not to be reduced.

Here another view with the traces started.

My current settings for this line

I also do not have any custom layers.

Application: KiCad PCB Editor

Version: 6.0.6-3a73a75311~116~ubuntu22.04.1, release build

	wxWidgets 3.0.5
	libcurl/7.81.0 OpenSSL/3.0.2 zlib/1.2.11 brotli/1.0.9 zstd/1.4.8 libidn2/2.3.2 libpsl/0.21.0 (+libidn2/2.3.2) libssh/0.9.6/openssl/zlib nghttp2/1.43.0 librtmp/2.3 OpenLDAP/2.5.12

Platform: Linux 5.15.0-40-generic x86_64, 64 bit, Little endian, wxGTK, ubuntu, x11

Build Info:
	Date: Jun 20 2022 15:50:05
	wxWidgets: 3.0.5 (wchar_t,wx containers,compatible with 2.8) GTK+ 3.24
	Boost: 1.74.0
	OCC: 7.5.2
	Curl: 7.83.1
	ngspice: 36
	Compiler: GCC 11.2.0 with C++ ABI 1016

Build settings:

Have you tried first drawing a short section of the differential pair before attempting to place the via’s?

Doing the pad breakout, adjusting the distance to get to the differential pair with, and then adjusting the width again to make room for the wider via’s all in may be a bit too much to do in one step.

As a workaround, you can also try to do the breakout and the via’s on the “south” side of the connector, and then move and rotate the tracks and via’s.

Yes, the traces start. Then having them placed and just starting vias, is the closest I can approach with the vias. If I put them closer to the traces ends on top, they jump to the other end of the traces on top of the pads.

Maybe the trace separation is closer than the via separation, and this may be a bug.

Ah, i cannot place vias DP vias anywhere in the current configuration. I thought it was just on that area.

I cannot place vias here too.

So, it looks like an issue with the clearance of these vias.

For me, starting a diff pair, letting it get to the gap width and then fanning it out t make room for via’s all in one step does work for me as expected. KiCad just widens the gap to make room for the via’s.


I just created a test differential pair in a random test project, Net class settings seem to still be default:

Your via’s are indeed very small (0.2032mm with 0.1mm hole) …

I also had a look at: PCB Editor / File / Board Setup / Design rules / Constraints / Copper / Minimum via diameter, but apparently these rules are not checked during track and via creation, but only during DRC and I’m out of inspiration.

Thanks for sharing your settings. I still could not fix this.

Yeah the via is very small. The hole of 0.1 mm was during this test.

Now I could put the vias by increasing the Via Size to at least 0.42 mm. It does not work if it is smaller. It may be related with another dimension that I am not aware of.

These are my Board Setup > Constraints by the way

Now if the via is not DP, then it can have smaller sizes.


I found out that what was preventing me to place vias on this case was the copper to hole clearence Reducing this value I could place the well formed vias between pins

This settgins here.


Now, i am not sure if ti is easy, but the DRC rule that is preventing me to place vias could be explicit in the line that says that DRC rule does not allow me to place the via. So it could have helped me to place those vias faster.

Sometimes I have had to route rest of the differential wires separately. KiCad is a bit stiff when routing.

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